參數(shù)資料
型號: HM5264805FTT-75
廠商: Hitachi,Ltd.
英文描述: 64M LVTTL interface SDRAM 133 MHz/100 MHz
中文描述: 6400 LVTTL接口SDRAM的133 MHz/100 MHz的
文件頁數(shù): 57/67頁
文件大小: 870K
代理商: HM5264805FTT-75
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
57
Mode Register Set Cycle
M
RAS
-
CAS
delay = 3
CAS
latency = 3
Burst length = 4
= V or V
IL
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
CKE
CS
RAS
CAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (output)
DQ (input)
@
Read Cycle/Write Cycle
H
/
I
7
&
8
'
@
/
I
0
M
N
H
P.
a
a+1 a+2 a+3
DQ (input)
/
7
@
&
'
/
%
-
.
-
6
>
DQ (output)
G
O
P
C
D
L
M
%
&
High-Z
b
b+3
b’
b’+1
b’+2
b’+3
l
valid
C: b’
RSA
code
lRCD
lRP
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
@
H
I
/
8
9
@
A
/
7
8
@
D
L
M
'
(
/
0
9
(
6
@
H
6
GH
P%
.
/
7
%
&
/
R: b
C: b
.
7
@
H
P
4
=
>
E
F
Output mask
V
IH
l = 3
CAS
latency = 3
Burst length = 4
= V or V
IH
IL
RCD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:b
C:b'
C:b"
b'+1 b"
b"+1 b"+2 b"+3
CKE
RAS
CAS
WE
CS
Address
DQMU/DQM,
DQ (input)
CLK
BS
=
F
O
<
=
E
=
E
F
O
=
E
F
O
R:a
C:a
R:b
C:b
C:b'
C:b"
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1b"+2 b"+3
H
I
H
I
A
J
8
A
I
J
7
8
@
A
I
A
I
J
8
@
A
I
I
J
@
H
I
I
J
@
H
I
9
:
B
0
9
B
0
8
9
/
0
8
9
/
0
8
A
1
:
'
0
1
'
0
0
1
'
0
5
>
F
G
4
5
=
F
+
4
5
=
5
=
>
F
G
5
=
F-
56
>
+
,
4
5
>
,
5
>
,
4
5$
%
-
6
#$
,
5
#
5$
-
5$
,
5$
%
$
$
$
%
'
(
)
!
)
(
)
1
:
(
)
1
'
(
1
'
(
K
L
B
K
L
B
J
K
B
J
K
J
A
B
J
K
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3
Read
Bank 3
Read
Bank 3
Bank 0
Precharge
Bank 3
Bank 0
Active
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 3
Write
Bank 3
Bank 0
Precharge
Bank 3
CKE
RAS
CS
CAS
WE
Address
DQM,
DQMU/DQML
BS
High-Z
High-Z
4
5
=
E
F
$
%
&
1
9
:
B
C
K
V
IH
V
IH
Read cycle
RAS
-
CAS
delay = 3
CAS
latency = 3
Burst length = 4
= V or V
IL
!
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HM5264405FTT-75 64M LVTTL interface SDRAM 133 MHz/100 MHz
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參數(shù)描述
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HM5264805FTT-B60 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz
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