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參數資料
| 型號： | HM628100LTTI-5SL |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit) |
| 中文描述： | 寬溫版本八米的SRAM（1024 - KWord的× 8位） |
| 文件頁數： | 10/17頁 |
| 文件大?。?/td> | 91K |
| 代理商： | HM628100LTTI-5SL |
HM628100I Series
8
Write Cycle
HM628100I
-5
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
55
—
ns
Address valid to end of write
50
—
ns
Chip selection to end of write
50
—
ns
5
Write pulse width
40
—
ns
4
Address setup time
0
—
ns
6
Write recovery time
0
—
ns
7
Data to write time overlap
25
—
ns
Data hold from write time
0
—
ns
Output active from end of write
5
—
ns
2
Output disable to output in high-Z
0
20
ns
1, 2
Write to output in high-Z
Notes: 1. t
, t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given device
and from device to device.
4. A write occures during the overlap of a low
CS1
, a high CS2, a low
WE
. A write begins at the latest
transition among
CS1
going low, CS2 going high,
WE
going low. A write ends at the earliest
transition among
CS1
going high, CS2 going low,
WE
going high. t
WP
is measured from the
beginning of write to the end of write.
5. t
CW
is measured from the later of
CS1
going low or CS2 going high to the end of write.
6. t
AS
is measured from the address valid to the beginning of write.
7. t
is measured from the earliest of
CS1
or
WE
going high or CS2 going low to the end of write
cycle.
0
20
ns
1, 2
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