參數(shù)資料
型號: HM628128DLFP-5
廠商: Hitachi,Ltd.
英文描述: Replaced by SN54LS158 : Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-CFP -55 to 125
中文描述: 1個M的SRAM(128 - KWord的× 8位)
文件頁數(shù): 7/20頁
文件大?。?/td> 124K
代理商: HM628128DLFP-5
HM628128D Series
7
AC Characteristics
(Ta = –20 to +70
°
C, V
CC
= 5.0 V
±
10%, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL
= 0.8 V, V
IH
= 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.5 V
Output timing reference level: 1.5 V
Output load: 1 TTL Gate+ CL (100 pF) (HM628128D-7)
1 TTL Gate+ CL (50 pF) (HM628128D-5)
(Including scope and jig)
Read Cycle
HM628128D
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
55
70
ns
Address access time
55
70
ns
Chip select access time
55
70
ns
55
70
ns
Output enable to output valid
30
35
ns
Output hold from address change
10
10
ns
Chip selection to output in low-Z
10
10
ns
2, 3
10
10
ns
2, 3
Output enable to output in low-Z
5
5
ns
2, 3
Chip deselection to output in high-Z
0
20
0
25
ns
1, 2, 3
0
20
0
25
ns
1, 2, 3
Output disable to output in high-Z
0
20
0
25
ns
1, 2, 3
相關(guān)PDF資料
PDF描述
HM628128DLFP-5SL Synchronous 4-Bit Counters 16-CDIP -55 to 125
HM628128DLFP-5UL 1 M SRAM (128-kword x 8-bit)
HM628128DLTS-7SL 1 M SRAM (128-kword x 8-bit)
HM628128DLTS-7UL 1 M SRAM (128-kword x 8-bit)
HM628128D 1 M SRAM (128-kword×8-bit)(1M靜態(tài)RAM (128k字×8位))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM628128DLFP-5SL 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit)
HM628128DLFP-5UL 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit)
HM628128DLFP-7 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit)
HM628128DLFP-7SL 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit)
HM628128DLFP-7UL 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit)