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參數(shù)資料
| 型號： | HM628128DLPI-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 1 M SRAM (128-kword X 8-bit) |
| 中文描述： | 1個M的SRAM（128 - KWord的× 8位） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 124K |
| 代理商： | HM628128DLPI-7 |
HM628128D Series
12
Low V
CC
Data Retention Characteristics
(Ta = –20 to +70
°
C)
Parameter
Symbol
Min
Typ
*
5
Max
Unit
Test conditions
*
4
V
CC
for data retention
V
DR
2.0
—
—
V
Vin
≥
0V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V
CS1
≥
V
CC
– 0.2 V
V
= 3.0 V, Vin
≥
0 V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V,
CS1
≥
V
CC
– 0.2 V
Data retention current
I
CCDR
*
1
—
1.0
50
μ
A
I
CCDR
*
2
I
CCDR
*
3
t
CDR
t
R
—
1.0
15
μ
A
μ
A
—
0.5
10
Chip deselect to data retention time
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. This characteristic is guaranteed only for L-version, 20
μ
A max. at Ta = –20 to +40
°
C.
2. This characteristic is guaranteed only for L-SL-version, 3
μ
A max. at Ta = –20 to +40
°
C.
3. This characteristic is guaranteed only for L-UL-version, 1
μ
A max. at Ta = –20 to +40
°
C.
4. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address,
WE
,
OE
,
CS1
, I/O) can be in the high impedance state.
If
CS1
controls data retention mode, CS2 must be CS2
≥
V
– 0.2 V or 0 V
≤
CS2
≤
0.2 V. The
other input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
5. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and specified loading, and not guaranteed.
6. t
RC
= read cycle time.
t
RC
*
6
—
—
ns
Low V
CC
Data Retention Timing Waveform (1)
(
CS1
Controlled)
V
CC
4.5 V
2.2 V
V
DR
0 V
CS1
t
CDR
t
R
CS1
≥
V
CC
– 0.2 V
Data retention mode
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| HM628128DLR-5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
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