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參數(shù)資料
| 型號： | HM628128DLR-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 |
| 中文描述： | 1個M的SRAM（128 - KWord的× 8位） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 124K |
| 代理商： | HM628128DLR-7 |
HM628128D Series
8
Write Cycle
HM628128D
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
55
—
70
—
ns
Address valid to end of write
50
—
60
—
ns
Chip selection to end of write
50
—
60
—
ns
5
Write pulse width
40
—
50
—
ns
4, 13
Address setup time
0
—
0
—
ns
6
Write recovery time
0
—
0
—
ns
7
Data to write time overlap
20
—
25
—
ns
Data hold from write time
0
—
0
—
ns
Output active from output in high-Z
5
—
5
—
ns
2
Output disable to output in high-Z
WE
to output in high-Z
, t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given
device and from device to device.
4. A write occurs during the overlap (t
) of a low
CS1
, a high CS2, and a low
WE
. A write begins
at the later transition of
CS1
going low, CS2 going high, or
WE
going low. A write ends at the
earlier transition of
CS1
going high, CS2 going low, or
WE
going high. t
WP
is measured from the
beginning of write to the end of write.
5. t
CW
is measured from
CS1
going low or CS2 going high to the end of write.
6. t
AS
is measured from the address valid to the beginning of write.
7. t
is measured from the earlier of
WE
or
CS1
going high or CS2 going low to the end of write
cycle.
8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
9. If the
CS1
goes low or CS2 going high simultaneously with
WE
going low or after
WE
going low,
the output remain in a high impedance state.
10.Dout is the same phase of the write data of this write cycle.
11.Dout is the read data of next address.
12.If
CS1
is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of the opposite phase to the outputs must not be applied to them.
13.In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem of
data bus contention. t
WP
≥
t
DW
min + t
WHZ
max
0
20
0
25
ns
1, 2, 8
0
20
0
25
ns
1, 2, 8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM628128DLR-7SL | Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 |
| HM628128DLR-7UL | Quadruple D-type Flip-Flops With Clear 20-LCCC -55 to 125 |
| HM628128DLT-5 | Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125 |
| HM628128DLT-5SL | Quadruple D-type Flip-Flops With Clear 16-CFP -55 to 125 |
| HM628128DLT-5UL | Arithmetic Logic Units/Function Generators 24-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM628128DLR-7SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
| HM628128DLR-7UL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
| HM628128DLT-5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
| HM628128DLT-5SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
| HM628128DLT-5UL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:1 M SRAM (128-kword x 8-bit) |
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