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參數(shù)資料
| 型號： | HM62G18512BP-5 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8M Synchronous Fast Static RAM(512k-word x 18-bit) |
| 中文描述： | 分同步快速靜態(tài)存儲器（為512k字× 18位） |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 121K |
| 代理商： | HM62G18512BP-5 |
HM62G18512 Series
20
Boundary Scan Order
Bit No.
Bump ID
Signal name
Bit No.
Bump ID
Signal name
1
5R
M2
27
2B
NC
2
6T
SA15
28
3A
SA6
3
4P
SA14
29
3C
SA3
4
6R
SA10
30
2C
SA13
5
5T
SA12
31
2A
SA0
6
7T
ZZ
32
1D
DQb0
7
7P
DQa0
33
2E
DQb1
8
6N
DQa1
34
2G
DQb2
9
6L
DQa2
35
1H
DQb3
SWEb
10
7K
DQa3
SWEa
K
36
3G
11
5L
37
4D
ZQ
SS
12
4L
38
4E
13
4K
K
G
39
4G
NC
14
4F
40
4H
NC
SWE
15
6H
DQa8
41
4M
16
7G
DQa7
42
2K
DQb8
17
6F
DQa6
43
1L
DQb7
18
7E
DQa5
44
2M
DQb6
19
6D
DQa4
45
1N
DQb5
20
6A
SA2
46
2P
DQb4
21
6C
SA1
47
3T
SA11
22
5C
SA5
48
2R
SA9
23
5A
SA4
49
4N
SA16
24
6B
SA18
50
2T
SA17
25
5B
SA8
51
3R
M1
26
Notes: 1. Bit number1 is the first scan bit to exit the chip.
2. The NC pads listed in this table are indeed no connects, but are represented in the boundary
scan register by a “Place Holder”. Placeholder registers are internally connected to V
SS
.
3. In Boundary scan mode, differential input K and
K
are referred to each other and must be at
opposite logic levels for reliable operation.
4. ZZ must remain at V
IL
during boundary scan.
5. In boundary scan mode, ZQ must be driven to V
DDQ
or V
SS
supply rail to ensure consistent results.
6. M1 and M2 must be driven to V
DD
or V
SS
supply rail to ensure consistent results.
3B
SA7
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