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參數(shù)資料
| 型號： | HM62V16100LTI-5SL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Wide Temperature Range Version |
| 中文描述： | 寬溫版本 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 215K |
| 代理商： | HM62V16100LTI-5SL |
HM62V16100I Series
Rev.2.00, Oct.06.2003, page 20 of 23
Low V
CC
Data Retention Characteristics
(Ta =
40 to +85
°
C)
Parameter
Symbol
Min
Typ*
5
Max
Unit
Test conditions*
3, 4
V
CC
for data retention
V
DR
1.5
3.6
V
Vin
≥
0 V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
0.2 V,
CS1
≥
V
CC
0.2 V or
(3)
LB
=
UB
≥
V
0.2 V,
CS2
≥
V
0.2 V,
CS1
≤
0.2 V
V
= 3.0 V, Vin
≥
0 V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
0.2 V,
CS1
≥
V
CC
0.2 V or
(3)
LB
=
UB
≥
V
0.2 V,
CS2
≥
V
0.2 V,
CS1
≤
0.2 V
Average value
Data retention current
I
CCDR
*
1
0.5
25
μ
A
I
CCDR
*
t
CDR
2
0
0.5
8
μ
A
ns
Chip deselect to data
retention time
See retention waveforms
Operation recovery time
Notes: 1. This characteristic is guaranteed only for L-version.
2. This characteristic is guaranteed only for L-SL version.
3.
BYTE
pin supported by only TSOP type.
BYTE
≥
V
CC
0.2 V or
BYTE
≤
0.2 V
4. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer,
LB
,
UB
buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address,
WE
,
OE
,
CS1
,
LB
,
UB
, I/O) can be in the
high impedance state. If
CS1
controls data retention mode, CS2 must be CS2
≥
V
0.2 V or 0
V
≤
CS2
≤
0.2 V. The other input levels (address,
WE
,
OE
,
LB
,
UB
, I/O) can be in the high
impedance state.
5. Typical values are at V
CC
= 3.0 V, Ta = +25
°
C and not guaranteed.
t
R
5
ms
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