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參數(shù)資料
| 型號： | HM62V16256CLTT-7SL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M SRAM (256-kword x 16-bit) |
| 中文描述： | 四米的SRAM（256 - KWord的x 16位） |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 76K |
| 代理商： | HM62V16256CLTT-7SL |
HM62V16256C Series
15
Low V
CC
Data Retention Characteristics
(Ta = –20 to +70
°
C)
Parameter
Symbol
Min
Typ
*
4
Max
Unit
Test conditions
*
3
V
CC
for data retention
V
DR
2.0
—
3.6
V
Vin
≥
0V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V
CS1
≥
V
CC
– 0.2 V or
(3)
LB
=
UB
≥
V
– 0.2 V,
CS2
≥
V
– 0.2 V,
CS1
≤
0.2 V
V
= 3.0 V, Vin
≥
0V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V,
CS1
≥
V
CC
– 0.2 V or
(3)
LB
=
UB
≥
V
– 0.2 V,
CS2
≥
V
– 0.2 V,
CS1
≤
0.2 V
Data retention current
I
CCDR
*
1
—
0.8
20
μ
A
I
CCDR
*
2
t
CDR
—
0.8
10
μ
A
Chip deselect to data
retention time
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. This characteristic is guaranteed only for L-version, 10
μ
A max. at Ta = –20 to +40
°
C.
2. This characteristic is guaranteed only for L-SL version, 5
μ
A max. at Ta = –20 to +40
°
C.
3. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer,
LB
,
UB
buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address,
WE
,
OE
,
CS1
,
LB
,
UB
, I/O) can be in the
high impedance state. If
CS1
controls data retention mode, CS2 must be CS2
≥
V
– 0.2 V or 0 V
≤
CS2
≤
0.2 V. The other input levels (address,
WE
,
OE
,
LB
,
UB
, I/O) can be in the high
impedance state.
4. Typical values are at V
CC
= 3.0 V, Ta = +25C and not guaranteed.
5. t
RC
= read cycle time.
t
R
t
RC
*
5
—
—
ns
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