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參數(shù)資料
| 型號： | HM62V16258BLTT-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M SRAM (256-kword x 16-bit) |
| 中文描述： | 四米的SRAM（256 - KWord的x 16位） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 74K |
| 代理商： | HM62V16258BLTT-7 |
HM62V16258B Series
7
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: V
IL
= 0.4 V, V
IH
= 2.2 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference levels: 1.4 V
Output load: 1 TTL + 30 pF (HM62V16258B-7) (Including scope and jig)
1 TTL + 100 pF (HM62V16258B-8) (Including scope and jig)
Read Cycle
HM62V16258B
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS
t
OE
t
OH
t
BA
t
CLZ
t
BLZ
t
OLZ
t
CHZ
t
BHZ
t
OHZ
70
—
85
—
ns
Address access time
—
70
—
85
ns
Chip select access time
—
70
—
85
ns
Output enable to output valid
—
40
—
45
ns
Output hold from address change
LB
,
UB
access time
10
—
10
—
ns
—
70
—
85
ns
Chip select to output in low-Z
LB
,
UB
enable to low-z
10
—
10
—
ns
2, 3
5
—
5
—
ns
2, 3
Output enable to output in low-Z
5
—
5
—
ns
2, 3
Chip deselect to output in high-Z
LB
,
UB
disable to high-Z
0
25
0
25
ns
1, 2, 3
0
25
0
25
ns
1, 2, 3
Output disable to output in high-Z
0
25
0
25
ns
1, 2, 3
相關(guān)PDF資料 |
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|---|---|
| HM62V16258BLTT-7SL | 4 M SRAM (256-kword x 16-bit) |
| HM62V16258BLTT-8 | 4 M SRAM (256-kword x 16-bit) |
| HM62V16258BLTT-8SL | 4 M SRAM (256-kword x 16-bit) |
| HM62V16258B | 4 M SRAM (256-kword ×16-bit)(4M靜態(tài)RAM (256k字 ×16位)) |
| HM62V16258CI | 4 M SRAM (256-kword ×16-bit)(4M靜態(tài)RAM (256k字 ×16位)) |
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