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參數(shù)資料
| 型號(hào)： | HM62W16255CJPI12 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Wide Temperature Range Version 4M High Speed SRAM (256-kword ⅴ 16-bit) |
| 中文描述： | 寬溫版本4分高速SRAM（256 - KWord的ⅴ16位） |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 87K |
| 代理商： | HM62W16255CJPI12 |
HM62W16255HCI Series
Rev.1, Nov. 2001, page 9 of 17
Write Cycle
HM62W16255HCI
-12
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
LBW
, t
UBW
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
12
—
ns
Address valid to end of write
8
—
ns
Chip select to end of write
8
—
ns
8
Write pulse width
8
—
ns
7
Byte select to end of write
8
—
ns
9, 10
Address setup time
0
—
ns
5
Write recovery time
0
—
ns
6
Data to write time overlap
6
—
ns
Data hold from write time
0
—
ns
Write disable to output in low-Z
3
—
ns
1
Output disable to output in high-Z
—
6
ns
1
Write enable to output in high-Z
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the
CS
or
LB
or
UB
low transition occurs simultaneously with the
WE
low transition or after the
WE
transition, output remains a high impedance state.
3.
WE
and/or
CS
must be high during address transition time.
4. If
CS
,
OE
,
LB
and
UB
are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. t
AS
is measured from the latest address transition to the latest of
CS
,
WE
,
LB
or
UB
going low.
6. t
WR
is measured from the earliest of
CS
,
WE
,
LB
or
UB
going high to the first address transition.
7. A write occurs during the overlap of low
CS
, low
WE
and low
LB
or low
UB
.
8. t
CW
is measured from the later of
CS
going low to the end of write.
9. t
LBW
is measured from the later of
LB
going low to the end of write.
10.
t
UBW
is measured from the later of
UB
going low to the end of write.
—
6
ns
1
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