參數(shù)資料
型號(hào): HM66AEB18202BP-60
英文描述: HM66AEB36102/HM66AEB18202 HM66AEB9402 Datasheet
中文描述: HM66AEB36102/HM66AEB18202 HM66AEB9402數(shù)據(jù)表
文件頁(yè)數(shù): 11/32頁(yè)
文件大?。?/td> 251K
代理商: HM66AEB18202BP-60
HM66AEB36102/18202/9402
Rev.0.0, Dec. 2002, page 9 of 30
Burst Sequence
Linear Burst Sequence Table
(HM66AEB36102/18202)
SA0
SA0
External address
0
1
1st internal burst address
1
0
Truth Table
Operation
K
LD
R/
W
DQ
WRITE cycle
Load address, input write data on
consecutive K and
K
rising edges
L
H
L
L
Data in
Input
data
D
A
(A1)
D
A
(A2)
Input
clock
K(t+1)
K
(t+1)
READ cycle
Load address, read data on
consecutive C and
C
rising edges
L
H
L
H
Data out
Output
data
Q
A
(A1)
Q
A
(A2)
Output
clock
C
(t+1)
C(t+2)
NOP (No operation)
L
H
Stopped
H
×
×
High-Z
STANDBY (Clock stopped)
Notes: 1. H: high level, L: low level,
×
: don’t care,
: rising edge.
2. Data inputs are registered at K and
K
rising edges. Data outputs are delivered at C and
C
rising
edges, except if C and
C
are high, then data outputs are delivered at K and
K
rising edges.
3. All control inputs in the truth table must meet setup/hold times around the rising edges (low to
high) of K and are registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that (K) = /(
K
) = (C) = /(
C
) when clock is stopped. This is not essential, but
permits most rapid restart by overcoming transmission line charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal
burst address in accordance with the linear burst sequence.
×
Previous state
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