參數(shù)資料
型號： HM66AEB36102BP-40
英文描述： HM66AEB36102/HM66AEB18202 HM66AEB9402 Datasheet
中文描述： HM66AEB36102/HM66AEB18202 HM66AEB9402數(shù)據(jù)表
文件頁數(shù)： 7/32頁
文件大小： 251K
代理商： HM66AEB36102BP-40
HM66AEB36102/18202/9402
Rev.0.0, Dec. 2002, page 5 of 30
Pin Descriptions
Name
I/O type Descriptions
SA0
SAn
Input
Synchronous address inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. Ball 2A is reserved for the next higher-order
address input on future devices. All transactions operate on a burst-of-two words (one
clock period of bus activity). SA0 is used as the lowest address bit for burst READ and
burst WRITE operations permitting a random burst start address on
×
18 and
×
36
devices. These inputs are ignored when device is deselected.
LD
Input
Synchronous load: This input is brought low when a bus cycle sequence is to be
defined. This definition includes address and READ / WRITE direction. All transactions
operate on a burst-of-two data (one clock period of bus activity).
Synchronous read / write input: When
LD
is low, this input designates the access type
(READ when R/
W
is high, WRITE when R/
W
is low) for the loaded address. R/
W
must
meet the setup and hold times around the rising edge of K.
R/
W
Input
BW
BWn
Input
Synchronous byte writes: When low, these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and
K
for each of the two rising edges comprising the
WRITE cycle. See Byte Write Truth Table for signal to data relationship.
K,
K
Input
Input clock: This input clock pair registers address and control inputs on the rising edge
of K, and registers data on the rising edge of K and the rising edge of
K
.
K
is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
C,
C
Input
Output clock: This clock pair provides a user-controlled means of tuning device output
data. The rising edge of C is used as the output timing reference for second output data.
The rising edge of
C
is used as the output reference for first output data. Ideally,
C
is
180 degrees out of phase with C. C and
C
may be tied high to force the use of K and
K
as the output reference clocks instead of having to provide C and
C
clocks. If tied high,
C and
C
must remain high and not to be toggled during device operation.
DOFF
Input
DLL disable: When low, this input causes the DLL to be bypassed for stable, low-
frequency operation.
ZQ
Input
Output impedance matching input: This input is used to tune the device outputs to the
system data bus impedance. DQ and CQ output impedance are set to 0.2
×
RQ, where
RQ is a resistor from this ball to ground. Alternately, this ball can be connected directly
to V
, which enables the minimum impedance mode. This ball cannot be connected
directly to V
SS
or left unconnected.
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the
JTAG function is not used in the circuit.
TMS
TDI
Input
TCK
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V
SS
if the JTAG
function is not used in the circuit.
相關(guān)PDF資料
PDF描述
HM66AEB36102BP-50 HM66AEB36102/HM66AEB18202 HM66AEB9402 Datasheet
HM66AEB36102BP-60 HM66AEB36102/HM66AEB18202 HM66AEB9402 Datasheet
HM66AEB36104BP-30 HM66AEB36104/HM66AEB18204 HM66AEB9404 Datasheet
HM66AEB36104BP-33 HM66AEB36104/HM66AEB18204 HM66AEB9404 Datasheet
HM66AEB36104BP-40 HM66AEB36104/HM66AEB18204 HM66AEB9404 Datasheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM66AEB36102BP-50 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AEB36102/HM66AEB18202 HM66AEB9402 Datasheet
HM66AEB36102BP-60 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AEB36102/HM66AEB18202 HM66AEB9402 Datasheet
HM66AEB36104BP-30 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AEB36104/HM66AEB18204 HM66AEB9404 Datasheet
HM66AEB36104BP-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AEB36104/HM66AEB18204 HM66AEB9404 Datasheet
HM66AEB36104BP-40 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HM66AEB36104/HM66AEB18204 HM66AEB9404 Datasheet
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