HM66AEB36102/18202/9402
Rev.0.0, Dec. 2002, page 24 of 30
TAP Controller Instruction Set
IR2
IR1
IR0
Instruction
Description
Notes
0
0
0
EXTEST
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register cells
at output balls are used to apply test vectors, while those at
input balls capture test results. Typically, the first test vector to
be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output drive is
turned on and the PRELOAD data is driven onto the output
balls.
1, 2
0
0
1
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into
the ID register when the controller is in capture-DR mode and
places the ID register between the TDI and TDO balls in shift-
DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in
the Test-Logic-Reset state.
0
1
0
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register,
all RAM outputs are forced to an inactive drive state (high-Z,
except CQ,
CQ
ball) and the boundary register is connected
between TDI and TDO when the TAP controller is moved to the
shift-DR state.
0
1
1
RESERVED
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
1
0
0
SAMPLE
(-PRELOAD)
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR state
loads the data in the RAMs input and I/O buffers into the
boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the
TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although
allowing the TAP to SAMPLE metastable input will not harm the
device, repeatable results cannot be expected. RAM input
signals must be stabilized for long enough to meet the TAPs
input data capture setup plus hold time (t
plus t
). The RAMs
clock inputs need not be paused for any other TAP operation
except capturing the I/O ring contents into the boundary scan
register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO balls.
1
0
1
RESERVED
1
1
0
RESERVED
1
1
1
BYPASS
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO.
This occurs when the TAP controller is moved to the shift-DR
state. This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal
operation.