參數(shù)資料
型號(hào)： HMP8170
廠商： Intersil Corporation
英文描述： NTSC/PAL Video Encoder
中文描述： NTSC / PAL視頻編碼器
文件頁(yè)數(shù)： 21/33頁(yè)
文件大?。?/td> 232K
代理商： HMP8170
21
TABLE 38. START V_BLANK HIGH REGISTER
SUB ADDRESS = 24
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-1
Reserved
0000000
B
0
MSB Assert BLANK
Output Signal
(Vertical)
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an output.
1
B
TABLE 39. END V_BLANK REGISTER
SUB ADDRESS = 25
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
(Vertical)
During normal operation, this 8-bit register specifies the line number (n) to start inputting pixel
input data (and what line number to start generating active output video) each odd field; for
even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
H
(note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
13
H
TABLE 40. FIELD CONTROL REGISTER 1
SUB ADDRESS = 26
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Field Detect
Window Size Low
This 8-bit register is cascaded with Field Detect Window Size High to form a 9-bit Field Detect
Window Size value. The value specifies the number of 1x clock cycles in the detection window
before and after the selected edge of VSYNC. It may range from 0 to 511. If the leading edge
of HSYNC occurs within the window, it is the start of an odd or even field, as specified by the
FIELD Detect Select bit. This register is ignored unless HSYNC and VSYNC are configured
as inputs.
80
H
TABLE 41. FIELD CONTROL REGISTER 2
SUB ADDRESS = 27
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-4
Half Line Count
Reset Value
These bits specify the value to load to the vertical half line counter when the selected edge of
VSYNC. The value is ignored when HSYNC and VSYNC are configured as outputs.
00000
B
2
VSYNC Edge
Select
This bit specifies whetherthe encoder uses the leading or trailing edge ofVSYNC to determine
the field and to reset the half line counter. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = leading edge
1 = trailing edge
0
B
1
FIELD Detect
Select
This bit specifies whether an odd or even field is starting when the leading edge of HSYNC
occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are
configured as inputs.
0 = odd field
1 = even field
0
B
0
Field Detect
Window Size High
This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window
Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs.
0
B
HMP8170, HMP8171, HMP8172, HMP8173
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HMP8170_03 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder
HMP8170CN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder
HMP8170EVAL1 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder
HMP8171 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder
HMP8171CN 制造商:Rochester Electronics LLC 功能描述:- Bulk
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