24
CLK
39
I/O
1x pixel clock input/output. As an input, this clock must be free-running and synchronous to
the clock signal on the CLK2 pin. As an output, this pin may drive a maximum of one LS TTL
load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not
driven, the circuit for this pin should include a 4-12k
pull up resistor connected to VAA.
CLK2
41
I
2x pixel clock input. This clock must be a continuous, free-running clock.
SCL
18
I
I
2
C interface clock input. The circuit for this pin should include a 4-6k
pull-up resistor
connected to VAA.
SA
19
I
I
2
C interface address select input.
SDA
20
I/O
I
2
C interface data input/output. The circuit for this pin should include a 4-6k
pull-up resistor
connected to VAA.
RESET
25
I
Reset control input. A logical zero for a minimum of four CLK cycles resets the device.
RESET must be a logical one for normal operation.
Y
3
O
Luminance analog current output. This output contains luminance video, sync, blanking, and
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5
load. If not used, it should be connected to GND.
C
7
O
Chrominance analog current output. This output contains chrominance video, and blanking
information. In analog YUV or RGB output mode, an alternate signal is generated (see Table
12). It is capable of driving a 37.5
load. If not used, it should be connected to GND.
NTSC/PAL 1
11
O
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5
load. If not used, it should be
connected to GND.
NTSC/PAL 2
15
O
Composite video analog current output. This output contains composite video, sync,
blanking, and information. In analog YUV or RGB output mode, an alternate signal is
generated (see Table 12). It is capable of driving a 37.5
load. If not used, it should be
connected to GND.
VREF
61
I/O
Voltage reference. An optional external 1.235V reference may be used to drive this pin. If
left floating, the internal voltage reference is used.
FS_ADJUST
62
Full scale adjust control. A resistor (RSET) connected between this pin and GND sets the
full-scale output current of each of the DACs.
COMP 1
64
Compensation pin. A 0.1
μ
F ceramic chip capacitor should be connected between this pin
and VAA, as close to the device as possible.
COMP 2
63
Compensation pin. A 0.1
μ
F ceramic chip capacitor should be connected between this pin
and VAA as close to the device as possible.
VAA
+5V power. A 0.1
μ
F ceramic capacitor, in parallel with a 0.01
μ
F chip capacitor, should be
used between each group of VAA pins and GND. These should be as close to the device as
possible.
GND
Ground
Pin Descriptions
(Continued)
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
HMP8170, HMP8171, HMP8172, HMP8173