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參數資料
| 型號： | HMP8172CN |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | NTSC/PAL Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP64 |
| 文件頁數： | 20/33頁 |
| 文件大小： | 232K |
| 代理商： | HMP8172CN |
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20
TABLE 33. CRC_283 REGISTER
SUB ADDRESS = 19
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Reserved
00
B
5-0
Line 283
WSS CRC Data
This register is read out serially after the 14 bits of NTSC WSS data, if WSS is enabled. It is
ignored during PAL WSS operation. Bit D0 is shifted out first.
111111
B
TABLE 34. START H_BLANK LOW REGISTER
SUB ADDRESS = 20
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
LSB Assert BLANK
Output Signal
(Horizontal)
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
H
. This
register is ignored unless BLANK is configured as an output.
4A
H
TABLE 35. START H_BLANK HIGH REGISTER
SUB ADDRESS = 21
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-2
Reserved
000000
B
1-0
MSB Assert BLANK
Output Signal
(Horizontal)
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020
H
. This
register is ignored unless BLANK is configured as an output.
11
B
TABLE 36. END H_BLANK REGISTER
SUB ADDRESS = 22
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
(Horizontal)
This 8-bit register specifies the horizontal count (in 1x clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000
H
. This register is ignored
unless BLANK is configured as an output.
7A
H
TABLE 37. START V_BLANK LOW REGISTER
SUB ADDRESS = 23
H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
LSB Assert BLANK
Output Signal
(Vertical)
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
H
(note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
03
H
HMP8170, HMP8171, HMP8172, HMP8173
相關PDF資料 |
PDF描述 |
|---|---|
| HMP8170 | NTSC/PAL Video Encoder |
| HMP8170CN | NTSC/PAL Video Encoder |
| HMP8171 | RESISTOR 2.4M OHM .25W CARB COMP |
| HMP8173 | NTSC/PAL Video Encoder |
| HMP8173CN | NTSC/PAL Video Encoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HMP8173 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8173CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP817XEVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8190 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8190CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
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