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參數(shù)資料
| 型號： | HMP9701CN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | AC’97 Audio Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 174K |
| 代理商： | HMP9701CN |
7
AC Link Powerdown
The AC-link interface can be placed in a low power mode by
setting PR4 = 1 in the Powerdown Register (see above). In
this mode, both BIT_CLK and SDATA_IN are forced to a
logic “l(fā)ow” voltage level.
As shown in Figure 7 BIT_CLK and SDATA_IN are driven
low immediately following the decode of the write to the Pow-
erdown Control/Status Register (26h) with PR4 = 1. Once
HMP9701 has been instructed to powerdown the AC Link, a
special “wake up” sequence is required to return the AC-Link
to active mode. Note: any valid slots of audio output samples
in the frame containing the AC Link powerdown command
will be dropped.
Waking up the AC-Link
There are 2 methods for bringing the HMP9701’s AC-link out
of powerdown mode. The first is a “warm reset” that pre-
serves reactivates the AC Link while preserving the contents
of the HMP9701 control registers. The second is a “Cold
Reset” that reactivates the digital interface while resetting
the control registers to their default values. Once the AC Link
has been powered up, its operational readiness will be indi-
cated via the Codec Ready bit in the audio input frame
(slot 0, bit 15).
Warm AC Link Reset
A warm reset will reactivate the HMP9701’s AC-link without
altering the current control register values. A warm reset is
generated by driving SYNC high for a minimum of 1
μ
s in the
absence of BIT_CLK. Within normal audio frames SYNC is a
synchronous HMP9701 BIT_CLK. However, in the absence of
BIT_CLK, SYNC functions as an asynchronous input that is
used to generate a warm reset. The activation of BIT_CLK will
not occur until after the falling edge (high to low transition) of
the “wake up” SYNC. Note: the HMP9701 will not respond to
a “warm reset” via the SYNC input for 4 audio frame times fol-
lowing the frame that triggered the powerdown.
Cold AC Link Reset
A cold reset is achieved by asserting RESET for a minimum
of 1
μ
s. By driving RESET low, BIT_CLK will be activated, the
AC-Link will return to normal operation, and all HMP9701
control registers will be initialized to their default values.
RESET is an asynchronous HMP9701 input. Note: the
HMP9701 will remain in the reset state as long as RESET is
asserted “l(fā)ow”.
Suggested Powerdown Sequences
Figure 8 illustrates the complete powerdown of the
HMP9701. Starting from normal operation, sequential writes
to the Powerdown Register are performed to powerdown one
codec section at a time. After powering down the converters
and the analog front end, a final write to PR4 is executed to
shut down the HMP9701’s digital interface (AC-link). The
part will remain in sleep mode with all its registers holding
their static values.
A warm reset can be used to wake up the AC link which can
then be used to sequentially power up each codec section.
Each section should be powered up sequentially, and the
Powerdown Control/Status register (26h) should be read to
verify that a powered up section is stable/ready before pre-
ceding to power up the next section as shown in Figures 8
and 9. Note: after a complete powerdown, care must be taken
to make sure the Analog Mixer (PR2, PR3) is powered up and
stable before preceding to power up the ADCs and DACs.
The Figure 9 illustrates an HMP9701 powerdown sequence
that will keep all the mixers operational with the static volume
settings contained in their associated registers. This power-
down scenario could be used to place the HMP9701 in low
power mode while preserving the capability to play a CD (or
external LINE_IN source) through the HMP9701 to the
speakers.
SLOT 12
PREVIOUS FRAME
TAG
WRITE
TO 26H
DATA
PR4 = 1
SLOT 12
TAG
SYNC
BCLK
SDATA_OUT
SDATA_IN
NOTE: BCLK not to scale.
FIGURE 7. AC-LINK POWERDOWN TIMING
NORMAL
ADCs
OFF
PR0
ANALOG
OFF PR2
OR PR3
AC LINK
OFF
PR4
POWER
DOWN
DACs
OFF
PR1
PR0= 1
PR1=1
PR2=1
PR4=1
WARM
RESET
PR2=0
AND
ANL=1
PR1=0
AND
DAC=1
PR0=0
AND
ADC=1
DEFAULT
COLD
RESET
CODEC
READY
=1
FIGURE 8. EXAMPLE OF SEQUENTIAL POWERDOWN
NORMAL
ADCs
OFF
PR0
AC LINK
OFF
PR4
POWER
DOWN
DACs
OFF
PR1
PR0=1
PR1=1
PR4=1
WARM
RESET
PR1=0
AND
DAC=1
PR0=0
AND
ADC=1
FIGURE 9. HMP9701 POWERDOWN/UP WITH ANALOG ALIVE
HMP9701
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