參數(shù)資料
型號: HPC36003
廠商: National Semiconductor Corporation
英文描述: High-Performance microControllers
中文描述: 高性能微控制器
文件頁數(shù): 36/36頁
文件大?。?/td> 467K
代理商: HPC36003
The following is the Military 883 Electrical Specification for HPC16083 and HPC16003 For latest information on RETS 16083X
contact NSC local sales office
DC Electrical Specifications Test Conditions VCC e 5V g10% (Unless Otherwise Specified) (Note 1)
Symbol
Parameter
Conditions
SBGRP 1
SBGRP 2
SBGRP 3
Units
Notes
a
25 C
a
125 C
b
55 C
Min
Max
Min
Max
Min
Max
VIH1
Logical ‘‘1’’ Input
RESET NMI CKI and WO
09
V
Voltage
B10–B13 B15
(VCC)(VCC)(VCC)
VIH2
All Inputs except Port A
07
V
(VCC)(VCC)(VCC)
VIH3
Port A VCC e 55V
465
V
(Note 2)
Port A VCC e 45V
395
V
(Note 2)
VIL1
Logical ‘‘0’’ Input
RESET NMI CKI and WO
01
V
Voltage
(VCC)(VCC)(VCC)
VIL2
All Inputs except Port A
02
V
(VCC)(VCC)(VCC)
VIL3
Port A VCC e 55V
07
V
(Note 3)
Port A VCC e 45V
05
V
(Note 3)
VOH2
Logical ‘‘1’’ Output
IOH eb7mA(A0–A15
24
V
Voltage
B10–B12 B15 CK2)
VOH3
IOH3 eb16 mA (B0–B9 B13–B14
24
V
P0–P3) WO (Open Drain)
VOH4
IOH eb6 mA (ST1 ST2)
24
V
VOH5
IOH eb1mA(A0–A15 B10–B12 B15)
When Used as an External
24
V
AddressData Bus
VOL2
Logical ‘‘0’’ Output
IOL e 3 mA (CK2 A0–A15 B10-B12 B15)
04
V
VOL3
Voltage
IOL e 05 mA (B0–B9 B13-B14 P0–P3
04
V
WO (Open Drain)
VOL4
IOL e 16 mA (ST1 ST2)
04
V
VOL5
IOL e 3mA(A0–A15 B10–B12 B15)
When Used as an External
04
V
AddressData Bus
IOZ
TRI-STATE Leakage VSS s VIN s VCC (WO Port A
g
5
g
5
g
5
m
A
Port B) VCC e 55V
ILI1
Input Leakage
VSS s VIN s VCC VCC e 55V
Current
(I1–I6 D0–D7 CKI
g
2
g
2
g
2
m
A
(Note 7)
RESET EXM EI)
ILI2
Input Pullup Current
VIN e 0(I0 I7 RDYHLD
b
50
b
3
b
50
b
3
b
50
b
3
m
A
(Note 7)
EXUI) VCC e 55V
ILI3
Port B12 Pulldown
VIN e VCC Port B12
171717
mA
during Reset
VCC e 55V
VRAM
RAM Keep Alive
Test Duration is 10 ms
25
V
Voltage
ICC1
Supply Current
FIN e 20 MHz RESET e VSS
55
mA
Dynamic
IOH e 0 mA IOL e 0 mA VCC e 55V
ICC2
Idle Mode Current
FIN e 20 MHz External Clock
35
mA
ICC
Halt Mode Current
NMI e VCC
222
mA
CIO
InputOutput
ftest e 10 MHz
20
pF
(Note 4)
Capacitance
IO Pin to Ground
SBGRP4
CI
Input Capacitance
ftest e 10 MHz
10
pF
(Note 4)
Input Pin to Ground
Note 1
Electrical end point testing (when required) for GroupsCD shall consist only of subgroups 1 2 9 and 10
Note 2
Port A VIH test limit includes 700 mV offset caused by output loads being on during Data Drive Time
Note 3
Port A VIL test limit includes 400 mV offset caused by output loads being on during Data Drive Time
Note 4
Verified at initial qual only
Note 7
Future revisions of this device will not have pullups on pins I0 I7 which will be tested to ILI1 conditions
9
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