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參數(shù)資料
| 型號： | HPC46083 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microControllers |
| 中文描述： | 高性能微控制器 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 467K |
| 代理商： | HPC46083 |
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20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 thru Figure 5 )VCC e 50V g10% unless otherwise specified TA e 0 Cto a70 C for
HPC46083HPC46003 b40 Cto a85 C for HPC36083HPC36003 b40 Cto a105 C for HPC26083HPC26003 b55 Cto
a
125 C for HPC16083HPC16003 (Continued)
Symbol and Formula
Parameter
Min
Max
Units
Note
tDC1ALER
Delay from CKI Rising
0
35
ns
(Notes 1 2)
Edge to ALE Rising Edge
tDC1ALEF
Delay from CKI Rising
0
35
ns
(Notes 1 2)
Edge to ALE Falling Edge
tDC2ALER e
tC
a
20
Delay from CK2 Rising
45
ns
(Note 2)
Edge to ALE Rising Edge
tDC2ALEF e
tC
a
20
Delay from CK2 Rising
45
ns
(Note 2)
Edge to ALE Rising Edge
tLL e
tC b 9
ALE Pulse Width
41
ns
tST e
tC b 7
Setup of Address Valid
18
ns
before ALE Falling Edge
tVP e
tC b 5
Hold of Address Valid
20
ns
after ALE Falling Edge
tARR e
tC b 5
ALE Falling Edge to RD Falling Edge
20
ns
tACC e tC a WS b 55
Data Input Valid after
145
ns
(Note 6)
Address Output Valid
tRD e
tC a WS b 65
Data Input Valid after
95
ns
RD Falling Edge
tRW e
tC a WS b 10
RD Pulse Width
140
ns
tDR e
tC b 15
Hold of Data Input Valid
060
ns
after RD Rising Edge
tRDA e tC b 15
Bus Enable after RD Rising Edge
85
ns
tARW e
tC b 5
ALE Falling Edge to
45
ns
WR Falling Edge
tWW e
tC a WS b 15
WR Pulse Width
160
ns
tV e
tC a WS b 5
Data Output Valid before
145
ns
WR Rising Edge
tHW e
tC b 5
Hold of Data Valid after
20
ns
WR Rising Edge
tDAR e
tC a WS b 50
Falling Edge of ALE
75
ns
to Falling Edge of RDY
tRWP e tC
RDY Pulse Width
100
ns
Address
Cycles
Read
Cycles
Write
Cycles
Ready
Input
Note
CL e 40 pF
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (tCKIR and TCKIL) on CKI input less than 25 ns
Note 2
Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later tHAE as long as (3tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait state and ready input
Note 4
WS (tWAIT) x (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC e 20 MHz with
one wait programmed
Note 5
Due to emulation restrictionsactual limits will be better
Note 6
This is guaranteed by design and not tested
4
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相關代理商/技術參數(shù) |
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|---|---|
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| HPC46083TXQ/OV30/SP108663 | 制造商:Texas Instruments 功能描述: |
| HPC46083TXQ/V30/SP108663 | 制造商:Texas Instruments 功能描述: |
| HPC46083XXX/F30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
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