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參數(shù)資料
| 型號(hào)： | HS574AT883 |
| 元件分類： | 串行ADC |
| 英文描述： | 12-bit Sampling A/D Converters |
| 中文描述： | 12位采樣的A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | HS574AT883 |
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8
R/C
CE
COWAIT FOR
BUS READ
CONVERSION
VIN
CDAC VOLTAGE
0 VOLTS
t(ACQ)
ACTIME
ACQUISITION TIME =
the input which will upset the buffer output and
may add error to the conversion itself.
Furthermore, the isolation of the input after the
acquisition time in the
HS574A/SP674A
allows
the user an opportunity to release the hold on an
external sample-and-hold and start it tracking
the next sample. This will increase system
throughput with the user's existing components.
When using an external S/H, the
HS574A/
SP674A
acts as any other 574–type device be-
cause the internal S/H is transparent. The sample/
hold function in the
HS574A/SP674A
is inher-
ent to the capacitor DAC structure, and its timing
characteristics are determined by the internally
generated clock. However, for multiplexer op-
eration, the internal S/H may eliminate the need
for an external S/H. The operation of the S/H
function is internal to the
HS574A/SP674A
and
is controlled through the normal R/C control line
(refer to
Figure 3
). When the R/C line makes a
negative transition, the
HS574A/SP674A
starts
the timing of the sampling and conversion. The
first two clock cycles are allocated to signal
Figure 3. Sample–and–Hold Function
Figure 1. Aperture Uncertainty
acquisition of the input by the CDAC (this time
is defined as t
). Following these two cycles,
the input sample is taken and held. The A/D
conversion follows this cycle with the duration
controlled by the internal clock cycle, which is
determined by the specific product model. Note
that because the sample is taken relative to the
R/C transition, t
is also the traditional “aper-
ture delay” of this internal sample and hold.
Since t
is measured in clock cycles, its
duration will vary with the internal clock
frequency. This results in T
= 2.9
μ
sec
±
1.1
μ
secs between units and over temperatures.
Offset, gain and linearity errors of the S/H cir-
cuit, as well as the effects of its droop rate, are
included in the overall specs for the
HS574A/
SP674A
.
USING THE SPX74A SERIES
Typical Interface Circuit
The
HS574A/SP674A
is a complete A/D con-
verter that is fully operational when powered up
and issued a Start Convert Signal. Only a few
external components are necessary.
Figure 4
depicts a typical interface circuit for operating
the
HS574A/SP674A
in a unipolar input mode.
Figure 5
depicts a typical interface circuit for
operating the
HS574A/SP674A
in a bipolar in-
put mode. Further information is given in the
following sections on these connections, but first
a few considerations concerning board layout to
achieve the best operation.
For each application of this device, strict atten-
tion must be given to power supply decoupling,
board layout (to reduce pickup between analog
V
ERROR
t
SAMPLE
POINT
V
ERROR
=
tdv
dt
25pF
R
EQ
= 4K
at any range.
T = R
EQ
x C
EQ
= 100ns.
Figure 2. Equivalent SP574A Input Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
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| HS574AU | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-Bit Sampling A/D Converters |
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| HS574AU883 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:12-bit Sampling A/D Converters |
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