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參數(shù)資料
| 型號： | HSP43481GC-25 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | POT 20K OHM 1/4 SQ CERM SL ST |
| 中文描述： | 8-BIT, DSP-DIGITAL FILTER, CPGA68 |
| 文件頁數(shù)： | 1/1頁 |
| 文件大小： | 95K |
| 代理商： | HSP43481GC-25 |
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
3-1
HSP43481
Digital Filter
Description
The HSP43481 is a video-speed Digital Filter (DF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of four filter cells cascaded internally
and a shift-and-add output stage, all in a single integrated
circuit. Each filter cell contains an 8 x 8 multiplier, three dec-
imation registers and a 26-bit accumulator which can add
the contents of any filter cell accumulator to the output stage
accumulator shifted right by eight-bits. The HSP43481 has a
maximum sample rate of 30MHz. The effective multiply-
accumulate (MAC) rate is 120MHz.
The HSP43481 can be configured to process expanded
coefficient and word sizes. Multiple devices can be cas-
caded for larger filter lengths without degrading the sample
rate or a single device can process larger filter lengths at
less than 30MHz with multiple passes. The architecture per-
mits processing filter lengths of over 1000 taps with the guar-
antee of no overflows. In practice, most filter coefficients are
less than 1.0, making even larger filter lengths possible. The
HSP43481 provides for unsigned or two’s complement arith-
metic, independently selectable for coefficients and signal
data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates of
1
/
2
,
1
/
3
or
1
/
4
the input sample rate. These registers also pro-
vide the capability to perform 2-D operations such as N x N
spatial correlations/convolutions for image processing appli-
cations.
Features
Four Filter Cells
0MHz to 30MHz Sample Rate
8-Bit Coefficients and Signal Data
26-Bit Accumulator per Stage
Filter Lengths Up to 1032 Tap
Expandable Coefficient Size, Data Size and Filter
Length
Decimation by 2, 3 or 4
Applications
1-D and 2-D FIR Filters
Radar/Sonar
Adaptive Filters
Echo Cancellation
Complex Multiply-Add
Sample Rate Converters
Ordering Information
PART NUMBER
TEMPERA-
TURE RANGE
0
o
C to +70
o
C
0
o
C to +70
o
C
0
o
C to +70
o
C
0
o
C to +70
o
C
0
o
C to +70
o
C
0
o
C to +70
o
C
PACKAGE
HSP43481JC-20
68 Lead PLCC
HSP43481JC-25
68 Lead PLCC
HSP43481JC-30
68 Lead PLCC
HSP43481GC-20
68 Lead PGA
HSP43481GC-25
68 Lead PGA
HSP43481GC-30
68 Lead PGA
September 1997
Block Diagram
TCCI
CIN0 - CIN7
FILTER
CELL 3
TCCO
COUT0 - COUT 7
ERASE
DCM0 - DCM1
DIENB
CIENB
COENB
MUX
CLK
ADR0 - 1
RESET
26
ADR0, ADR1
2
CLK
RESET
SHADD
SENBH
SENBL
OUTPUT
STAGE
8
V
CC
V
SS
DIN0 - DIN7 TCS
2
FILTER
CELL 2
26
8
8
FILTER
CELL 1
26
8
8
FILTER
CELL 0
26
8
8
8
5
4
2
26
8
4
8
26
D
File Number
2759.4
NOT RECOMMENDED FOR NEW DESIGNS
See HSP43881 or
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP43481GC-30 | Digital Filter |
| HSP43481JC-20 | Digital Filter |
| HSP43481JC-25 | Digital Filter |
| HSP43481JC-30 | Digital Filter |
| HSP43481 | Digital Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43481GC-30 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43481GM-20/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43481GM-20/883 WAF | 制造商:Harris Corporation 功能描述: |
| HSP43481GM-25/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43481JC-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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