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參數(shù)資料
| 型號： | HSP43881GC-30 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Digital Filter |
| 中文描述： | 8-BIT, DSP-DIGITAL FILTER, CPGA85 |
| 封裝： | PGA-85 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大?。?/td> | 148K |
| 代理商： | HSP43881GC-30 |
21
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Waveforms
FIGURE 8. CLOCK AC PARAMETERS
Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE,
RESET,DCM0-1, ADRO-2, TCS, TCCI, SHADD
FIGURE 9. INPUT SETUP AND HOLD
SUM-25, COUTO-7, TCCO are assumed not to be in high-
impedance state.
FIGURE 10. SUM0-25, COUT0-7, TCCO OUTPUT DELAYS
FIGURE 11. OUTPUT RISE AND FALL TIMES
FIGURE 12. OUTPUT ENABLE, DISABLE TIMING
NOTE: AC Testing: Inputs are driven at 3.0V for Logic and “1” and
0.0V for Logic “0”. Input and output timing measurements are made
at 1.5 for both a Logic “1” and “0”. CLK is driven at 4.0 and 0V and
measured at 2.0V.
FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM
CLK
2.0V
2.0V
2.0V
t
CP
t
CH
t
CL
0.0V
CLK
2.0V
INPUT
0.0V
1.5V
1.5V
3.0V
4.0V
t
IS
t
IH
CLK
SUM0-25
COUT0-7
TCCO
2.0V
1.5V
t
ODC,
t
ODS
2.0V
0.8V
t
OR
t
OF
HIGH
IMPEDANCE
1.5V
1.7V
1.3V
HIGH
IMPEDANCE
1.5V
SUM0-25
COUT0-7
TCCO
SENBL
SENBH
COENB
t
ODD
t
OED
1.5V
3.0V
0.0V
INPUT
1.5V
DEVICE
UNDER
TEST
OUTPUT
HSP43881
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP43881JC-20 | Digital Filter |
| HSP43881JC-25 | Digital Filter |
| HSP43881JC-30 | Digital Filter |
| HSP43881 | Digital Filter |
| HSP43881883 | Digital Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43881GM-25/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43881JC-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HSP43881JC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43881JC-30 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43881QM-20/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
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