參數(shù)資料
型號： HSP50214BVI
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁數(shù)： 11/60頁
文件大?。?/td> 573K
代理商： HSP50214BVI
3-11
See Figures 4-7 for an interpolated input example, detailing
the associated spectral results.
Interpolation Example:
The specifications for the interpolated input example are:
CLKIN = 40MHz
Input Sample Rate = 5 MSPS
PROCCLK = 28MHz
Interpolate by 8, Decimate by 10
Desired 85dB dynamic range output bandwidth = 500kHz
Input Level Detector
The Input Level Detector Section measures the average
magnitude error at the PDC input for the microprocessor by
comparing the input level against a programmable
threshold and then integrating the result. It is intended to
provide a gain error for use in an AGC loop with either the
RF/IF or A/D converter stages (see Figure 8). The AGC
loop includes Input Level Detector, the microprocessor and
an external gain control amplifier (or attenuator). The input
samples are rectified and added to a threshold
programmed via the microprocessor interface, as shown in
Figure 9. The bit weighting of the data path through the
input threshold detector is shown in Figure 10. The
threshold is a signed number, so it should be set to the
inverse of the desired input level. The threshold can be set
to zero if the average input level is desired instead of the
error. The sum of the threshold and the absolute value of
the input is accumulated in a 32-bit accumulator. The
accumulator can handle up to 2
18
samples without
overflow. The integration time is controlled by an 18-bit
counter. The integration counter preload (ICPrel) is
programmed via the microprocessor interface through
Control Word 1. Only the upper 16 bits are programmable.
The 2 LSBs are always zero. Control Word 1, Bits 29-14
are programmed to:
where N is the desired integration period, defined as the
number of input samples to be integrated. N must be a
multiple of 4: [0, 4, 8, 12, 16 .... , 2
18
].
ICPrel
N
( )
4
1
+
=
(EQ. 1)
FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION
Without Interpolation, the CIC bypass path exceeds the HB/FIR filter
input sample rate and the CIC filter path will not yield the desired
85dB dynamic range band width of 500kHz.
FIGURE 4. STATEMENT OF THE PROBLEM
FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION
APPROACH
I
IN(13:0)
INPUT_FMT
INPUT_THRESH
INTG_MODE
INTG_INTEVAL
ENI
LEVEL
DETECT
R
R
INPUT_MODE
NCO
R
R
DELAY 3
DELAY 3
GAINADJ(2:0)
S
C
CONTROL WORD 0
CONTROL
LOGIC
CONTROL WORD 1
CLKIN
Controlled via microprocessor interface.
See NCO Section for more details.
INPUT_THRESH
INTG_MODE
INTG_INTEVAL
INTERP
INPUT
FORMAT
BYPASS
M
INPUT LEVEL DETECTOR
STATUS (0)
∑
LIMIT
4
3
EN
4
14
14
18
18
15
15
CIC
FILTER
HB/FIR FILTER
5MHz
500kHz = 85dB
BANDWIDTH
(NOT ACHIEVED
WITH CIC FILTER
PATH)
M
MAX. f
S
= 4MHz
(EXCEEDED IN
BYPASS PATH)
MIN. R = 4
BYPASS
PROCCLK = 28MHz
CLKIN = 5MHz
CIC FILTER
R =
↓
10
↑
8 (0 STUFF) = 40MHz
500kHz = 85dB
BANDWIDTH
4MHz
HB/FIR FILTER
5MHz
CLKIN = 40MHz
HSP50214B
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