HT7070A
Ta=25 C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DET
Hi
Lo Detectable Voltage
6.65
7
7.35
V
Lo
Hi Detectable Voltage
6.783
7.35
8.085
V
V
HYS
Hysteresis Width
0.02
V
DET
0.05
V
DET
0.1
V
DET
V
I
DD
Operating Current
8
No load
4
7
A
V
DD
Operating Voltage
2.1
24
V
I
OL
V
Output Sink Current
5
V
OUT
=0.5V
5
10
mA
T
DET
A
Temperature Coefficient
0 C<Ta<70 C
0.9
mV/ C
HT70XX
7
May 3, 2000
Functional Description
The HT70XX series is a set of voltage detectors
equipped with a high stability voltage reference
which is connected to the negative input of a
comparator
denoted as V
REF
in the following
figure for NMOS output voltage detector.
When the voltage drop to the positive input of
the comparator (i,e,V
B
) is higher than V
REF
,
VOUT goes high, M1 turns off, and V
B
is ex-
pressed as V
BH
=VDD (RB+RC)/(RA+RB+RC).
If VDD is decreased so that V
B
falls to a value
less than V
REF
, the comparator output inverts
from high to low, VOUT goes low, V
C
is high, M1
turns on, RC is bypassed, and V
B
becomes:
V
BL
=VDD RB/(RA+RB), which is less than
V
BH.
By so doing, the comparator output will
stay low to prevent the circuit from oscillating
when V
B
V
REF.
If VDD falls below the minimum operating volt-
age, the output becomes undefined. When VDD
goes from low to VDD RB/(RA+RB) > V
REF
, the
comparator output and VOUT goes high.
The detectable voltage is defined as:
V
DET
( ) =RA
RB
RB
RC
RC
V
REF
The release voltage is defined as:
V
DET
(+) =RA
RB
RB
V
REF
The hysteresis width is:
V
HYS
= V
DET
(+)
V
DET
( )
The figure demonstrates the NMOS output
type with positive output polarity (VOUT is
normally open, active low). The HT70XX series
also supplies options for other output types
with active high outputs. Application circuits
shown are examples of positive output polarity
(normally open, active low) unless otherwise
specified.
! !
"
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NMOS output voltage detector (HT70XXA)
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