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參數(shù)資料
| 型號(hào)： | HT9032 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Calling Line Identification Receiver |
| 中文描述： | 來電線路識(shí)別接收器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 222K |
| 代理商： | HT9032 |
Pin Description
Pin Name
I/O
Description
Power Inputs
VDD
Power-VDD is the input power for the internal logic.
VSS
Ground-VSS is ground connection for the internal logic.
PDWN
I
A logic 1 on this pin puts the chip in power down mode. When a logic 0 is on
this pin, the chip is activated. This is a schmitt trigger input.
Clock
X1
I
A crystal or ceramic resonator should be connected to this pin and X2.
This pin may be driven from an external clock source.
X2
O
A crystal or ceramic resonator should be connected to this pin and X1.
Ring Detections
RDET1
I
It detects ring energy on the line through an attenuating network and enables
the oscillator and ring detection. This is a schmitt trigger input.
RDET2
I
It couples the ring signal to the precision ring detector through an attenuating
network.RDET= 0 ifavalidringsignalisdetected.Thisisaschmitttriggerin-
put.
RTIME
I/O
An RC network may be connected to this pin in order to hold the pin voltage be-
low 2.2V between the peaks of the ringing signal. This pin controls internal
power up and activates the partial circuitry needed to determine whether the
incoming ring is valid or not. The input is a schmitt trigger input. The output
cell structure is an NMOS output.
FSK Signal Inputs
TIP
I
This input pin is connected to the tip side of the twisted pair wires. It is inter-
nally biased to 1/2 V
DD
when the device is in power up mode. This pin must be
DC isolated from the line.
RING
I
This input pin is connected to the ring side of the twisted pair wires. It is inter-
nally biased to 1/2 V
DD
when the device is in power up mode. This pin must be
DC isolated from the line.
Detection Results
RDET
O
This open drain output goes low when a valid ringing signal is detected. When
connected to PDWN pin, this pin can be used for auto power up.
CDET
O
This open drain output goes low indicating that a valid carrier is present on the
line. A hysteresis is built-in to allow for a momentary drop out of the carrier.
When connected to PDWN pin, this pin can be used for auto power up.
DOUT
O
This pin presents the output of the demodulator whenever CDET pin is low.
This data stream includes the alternate 1 and 0 pattern, the marking, and
the data. At all other times, this pin is held high.
HT9032
3
April 6, 2000
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT9032A(16DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HT9032A(16SOP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HT9032B | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Calling Line Identification Receiver |
| HT9032B(8DIP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| HT9032B-A | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Calling Line Identification Receiver |
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