參數(shù)資料
型號(hào): HT95AXXX
廠商: Holtek Semiconductor Inc.
英文描述: I/O Type Phone 8-Bit MCU
中文描述: I / O型電話8位微控制器
文件頁(yè)數(shù): 19/48頁(yè)
文件大小: 360K
代理商: HT95AXXX
HT95AXXX
Rev. 1.20
19
May 26, 2004
Each I/O line has its own control register (PAC, PBC,
PDC, PEC, PFC, PGC) to control the input/output con-
figuration. With this control register, CMOS output or
Schmitt trigger input can be reconfigured dynamically
under software control. To make one I/O line to function
as an input line, the corresponding latch of the control
register must be written with a 1 . The pull-high resis-
tance shows itself automatically if the pull-high option is
selected. The input source also depends on the control
register. If the control register bit is 1 , the input will
read the pad state. If the control register bit is 0 , the
contents of the latches will move to the internal bus. The
latter is possible in the read-modify-write instruction.
For output function, CMOS is the only configuration.
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H,
18H, 1AH, 34H or 36H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. They are selected by mask option per bit.
There is a pull-high option available for all I/O lines.
Once the pull-high option of an I/O line is selected, the
I/O lines have pull-high resistor. Otherwise, the pull-high
resistor is absent. It should be noted that a non-pull-high
I/O line operating in input mode may cause a floating
state.
I/O port pull-high, wake-up function are selected by
mask option
I/O Port
Output
Input
Supported for HT95AXXX
Pull-high Resistor
Wake-up Function
400/P
300/P
200/P
100/P
PA7~PA0
CMOS
Selected per bit
Selected per bit
PB7~PB0
CMOS
Selected per bit
PD3~PD0
CMOS
Selected per nibble
PD7~PD4
CMOS
Selected per nibble
PE3~PE0
CMOS
Selected per nibble
PE7~PE4
CMOS
Selected per nibble
PF7~PF0
CMOS
Selected per nibble
PG3~PG0
CMOS
Selected per nibble
Note:
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Input/Output Ports
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