參數(shù)資料
型號(hào)： HT95CXXX
廠商： Holtek Semiconductor Inc.
英文描述： CID Type Phone 8-Bit MCU
中文描述： 刑事偵緝式電話8位微控制器
文件頁(yè)數(shù)： 25/51頁(yè)
文件大?。?/td> 384K
代理商： HT95CXXX
HT95CXXX
Rev. 1.50
25
May 26, 2005
3
8
E
3
6
3
%
0
Ring or Line Reversal Detect
When no signal is present on the telephone line, RDET1
will be at GND and RTIME is pulled to VDD by R1. If a
line reversal occurs, the RDET1 pin will become high.
This causes RTIME and internal signal R_DET to be
pulledlow.TheC1andR1ensurethattheR_DETsignal
islowduringsuchatime,sothatprocessorcandetectit.
When a ring occurs on the line, internal signal R_DET is
permanently low, indicating the envelope of the ring. If
the frequency of the ring must be measured, C1 may be
removed, RTIME and R_DET inverter follow RDET1.
TheflagRDETFwillgohighwhentheR_DETsignalfall-
ing edge is detected. This may cause a peripheral inter-
rupt if RMSK is 0 and the peripheral interrupt is enabled
(EPERI=1).
FSK Data Output
The FSK decoder will decode the FSK signal on the TIP
and RING line and produce two kinds of data formats,
the serial data and the 8-bit packet data. It also provides
the FSK carrier detection signal.
To enable the FSK decoder, the F_PWDN should be
written as 0. Once the FSK carrier signal is detected, the
flag CDETF will be set to 1. This may cause a peripheral
interrupt if CMSK is 0 and the peripheral interrupt is en-
abled.
The serial FSK data is present in two formats: RAW data
and COOK data, and could be monitored by the flag
DOUT, DOUTC, respectively.
The flag DOUTpresents the output of the decoder when
the decoder is at operation mode. This data stream in-
cludes the alternate 1 and 0 pattern, the marking and
the data.
The flag DOUTC presents the output of the decoder
when the decoder is at operation mode. This data
stream is like the DOUT flag but does not include the al-
ternate 1 and 0 pattern.
If the FSK data is not detected, the DOUT and DOUTC
are held high.
Beside the serial data, the decoder also provides FSK
packet data. When decoder receives an FSK signal, it
will packet 10 bits data to 8 bits data, the first and 10th
bits will be discarded. When the 8-bit packet data is
valid, it will be stored in the FSK data register FSKD, the
FSK packet data interrupt flag FSKF will be set to 1. This
may cause a peripheral interrupt if FMSK is 0 and the
peripheral interrupt is enabled. The FSK packet source
could be DOUT or DOUTC, selected by FSKSEL. Note
that the start bit of the 10 packet bit should be 0, so the
MARK signal (one of the FSK data signals) will not be
packeted.
To detect the carrier signal or decode the serial data or
packet 10-bit data to 8-bit data, the operation mode of
the controller must be selected in Normal mode (proces-
sor running with 3.58MHz). When the operation mode is
Green or Sleep, FSK decoder will decode the wrong sig-
nal. However, when the operation mode is Green or
Sleep mode and the FSK decoder is at power down
mode (F_PWDN=1), the ring and line reversal detect is
still functional.
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Note: * If the flag FSKSEL=1, the sync signal data will not be packeted.
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