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參數(shù)資料
| 型號(hào)： | HV623 |
| 廠商： | Supertex, Inc. |
| 英文描述： | 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver |
| 中文描述： | 32通道128級(jí)振幅灰色陰影顯示列驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | HV623 |
12-130
HV623
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
N/C
V
CTL
R
CTL
SC (Shift Clock)
LVGND
DIR
V
DD
(Digital)*
D
7
D
6
D
5
D
4
D
3
D
2
D
1
N/C
LVGND
N/C
LC (Load Count)
N/C
CC (Count Clock)
CSO
N/C
64-Pin PG Package
Pin
Function
1
HV
OUT
1
2
HV
OUT
2
3
HV
OUT
3
4
HV
OUT
4
5
HV
OUT
5
6
HV
OUT
6
7
HV
OUT
7
8
HV
OUT
8
9
HV
OUT
9
10
HV
OUT
10
11
HV
OUT
11
12
HV
OUT
12
13
HV
OUT
13
14
HV
OUT
14
15
HV
OUT
15
16
HV
OUT
16
17
HVGND
18
V
R
19
V
PP
20
N/C
21
V
DD
(Analog)*
22
CSI
Pin Configuration
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Function
V
PP
N/C
V
R
HVGND
HV
OUT
17
HV
OUT
18
HV
OUT
19
HV
OUT
20
HV
OUT
21
HV
OUT
22
HV
OUT
23
HV
OUT
24
HV
OUT
25
HV
OUT
26
HV
OUT
27
HV
OUT
28
HV
OUT
29
HV
OUT
30
HV
OUT
31
HV
OUT
32
Package Outlines
*Analog V
and digital V
may be connected
separately for better noise immunity.
3-Sided Plastic QFP 64-pin Gullwing Package
top view
Index
1
24
64
41
25
40
Theory of Operation
The HV623 has two primary functions:
1) Loading data from the data bus and,
2) Gray-shade conversion
(converting latched data to output voltages).
Since the device was developed initially for flat panel displays, the
operation will be described in terms that pertain to that technol-
ogy. As shown by the Typical Drive Scheme, several HV623
packages are mounted at the top and bottom of a display panel.
Data exists on a 7-bit bus (adjacent PC board traces) at top and
bottom. The D1 through D7 inputs of each chip take data from the
bus when either a CSI or CSO pulse is present at the chip. These
pulses therefore act as a combination CHIP SELECT and LOCA-
TION STROBE. Because of the way the chip HV
OUT
pins are
sequenced, data on the bus at the bottom of the display panel will
be entered into the left-most chip as HV
OUT
1
,
HV
OUT
2
,
etc. up to
HV
OUT
32. The CSI pulse will accomplish this with DIR = High.
Loading Data from Data Bus
Here is the full data-entry sequence:
1) The microcontroller puts data on the bus (7 bits)
2) To enter the data into the 32 sets of 7 latches on the first chip,
the shift clock rises. This positive transition is combined with
the CSI pulse and is generated only once to strobe the data into
the first set of latches. (These latches eventually send data to
the HV
OUT
1). The data on the bus then changes, the shift clock
falls, and this negative transition is combined with the CSI
pulse, which is now propagated internally, to strobe the new
data into the next set of 7 latches (which will end up as
HV
OUT
2). This internal CSI pulse therefore runs at twice the
shift clock rate.
3) When the last set of 7 latches in the first chip has been loaded
(HV
OUT
32), the CSI pulse leaves chip 1 and enters chip 2. The
exit pin is called CSO and the chip 2 entry pin is CSI . For chips
at the top of the panel things are reversed: DIR is low, entry pins
are CSO and exit pins are CSI , because the data-into-latches
sequence is in descending order, HV
OUT
32 down to HV
OUT
1.
4) The buses may of course be separate, and data can be strobed
in on an interleaved basis, etc., but those complications will be
left to systems designers.
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