參數(shù)資料
型號(hào): HW-V5-ML510-G
廠商: Xilinx Inc
文件頁數(shù): 3/91頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR VIRTEX-5 ML510
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® -5
類型: FPGA
適用于相關(guān)產(chǎn)品: XC5VFX130T-2FFG1738CES
所含物品: 評(píng)估平臺(tái),小型閃存卡,DDR2 DImm,LCD 顯示器
相關(guān)產(chǎn)品: XC5VFX130T-2FFG1738I-ND - IC FPGA VIRTEX-5FX 130K 1738FBGA
XC5VFX130T-2FFG1738C-ND - IC FPGA VIRTEX-5FX 130K 1738FBGA
XC5VFX130T-1FFG1738I-ND - IC FPGA VIRTEX-5FX 130K 1738FBGA
XC5VFX130T-1FFG1738C-ND - IC FPGA VIRTEX-5FX 130K 1738FBGA
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
11
Table 17: Processor Block DMA0 Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMDMA0LLCLK
1.256
1.42
1.665
ps
TCK_DATA
CPMDMA0LLCLK
1.312
1.472
1.712
ps
TCONTROL_CK
CPMDMA0LLCLK
0.453
0.558
0.716
ps
TDATA_CK
CPMDMA0LLCLK
–0.105
–0.104
ps
Table 18: Processor Block DMA1 Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMDMA1LLCLK
1.127
1.266
1.474
ps
TCK_DATA
CPMDMA1LLCLK
1.266
1.418
1.645
ps
TCONTROL_CK
CPMDMA1LLCLK
0.447
0.555
0.717
ps
TDATA_CK
CPMDMA1LLCLK
–0.014
0.01
0.046
ps
Table 19: Processor Block DMA2 Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMDMA2LLCLK
1.101
1.235
1.437
ps
TCK_DATA
CPMDMA2LLCLK
1.127
1.262
1.463
ps
TCONTROL_CK
CPMDMA2LLCLK
0.771
0.924
1.155
ps
TDATA_CK
CPMDMA2LLCLK
0.135
0.142
0.168
ps
Table 20: Processor Block DMA3 Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMDMA3LLCLK
1.094
1.242
1.462
ps
TCK_DATA
CPMDMA3LLCLK
1.056
1.184
1.376
ps
TCONTROL_CK
CPMDMA3LLCLK
0.636
0.767
0.965
ps
TDATA_CK
CPMDMA3LLCLK
0.087
0.119
0.116
ps
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