Application Information
(Continued)
POWER DISSIPATION
Power dissipation is a major concern when using any power
amplifier and must be thoroughly understood to ensure a
successful design. Equation 1 states the maximum power
dissipation point for a single-ended amplifier operating at a
given supply voltage and driving a specified output load.
P
DMAX
= (V
DD
)
2
/ (2
π
2
R
L
)
(1)
Since the
HWD
21
11 has two operational amplifiers in one
package, the maximum internal power dissipation point is
twice that of the number which results from Equation 1. Even
with the large internal power dissipation, the
HWD
21
11 does
not require heat sinking over a large range of ambient tem-
perature. From Equation 1, assuming a 5V power supply and
a 32
load, the maximum power dissipation point is 40mW
per amplifier. Thus the maximum package dissipation point
is 80mW. The maximum power dissipation point obtained
must not be greater than the power dissipation predicted by
Equation 2:
P
DMAX
= (T
JMAX
T
A
) /
θ
JA
(2)
For the MSOP package,
θ
JA
= 194C/W, and for the LD
package,
θ
JA
= 63C/W. T
JMAX
= 150C for the
HWD
21
11. For
a given ambient temperature, T
A
, of the system surround-
ings, Equation 2 can be used to find the maximum internal
power dissipation supported by the IC packaging. If the
result of Equation 1 is greater than that of Equation 2, then
either the supply voltage must be decreased, the load im-
pedance increased, or T
reduced. For the MSOP package
in a typical application of a 5V power supply and a 32
load,
the maximum ambient temperature possible without violating
the
maximum
junction
temperature
134.5C. This assumes the device operates at maximum
power dissipation and uses surface mount packaging. Inter-
nal power dissipation is a function of output power. If typical
operation is not around the maximum power dissipation
point, operation at higher ambient temperatures is possible.
Refer to the
Typical Performance Characteristics
curves
for power dissipation information for lower output power
levels.
is
approximately
EXPOSED-DAP PACKAGE PCB MOUNTING
CONSIDERATION
The
HWD
21
11’s exposed-dap (die attach paddle) package
(LD) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper traces, ground plane, and surrounding air.
The LD package should have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad may be con-
nected to a large plane of continuous unbroken copper. This
plane forms a thermal mass, heat sink, and radiation area.
However, since the
HWD
21
11 is designed for headphone ap-
plications, connecting a copper plane to the DAP’s PCB
copper pad is not required. The
HWD
21
11
’s Power Dissipation
vs Output Power Curve in the
Typical Performance Char-
acteristics
shows that the maximum power dissipated is just
45mW per amplifier with a 5V power supply and a 32
load.
Further detailed and specific information concerning PCB
layout, fabrication, and mounting an LD (LLP) package is
available from
CSMSC
Semiconductor’s Package Engineer-
ing Group under application note AN1187.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and
power supply pins should be as close to the device as
possible. The value of the bypass capacitor directly affects
the
HWD
21
11’s half-supply voltage stability and PSRR. The
stability and supply rejection increase as the bypass capaci-
tor’s value increases. Typical applications employ a 5V regu-
lator with 10μF and a 0.1μF bypass capacitors which aid in
supply stability, but do not eliminate the need for bypassing
the supply nodes of the
HWD
21
11. The selection of bypass
capacitors, especially C
, is thus dependent upon desired
low frequency PSRR, click and pop performance, (explained
in the section,
Proper Selection of External Components
),
system cost, and size constraints.
SHUTDOWN FUNCTION
In order to reduce power consumption while not is use, the
HWD
21
11 features amplifier bias circuitry shutdown. This shut-
down function is activated by applying a logic high to the
SHUTDOWN pin. The trigger point is 1.4V minimum for a
logic high level, and 0.4V maximum for a logic low level. It is
best to switch between ground and V
to ensure optimal
shutdown operation. By switching the SHUTDOWN pin to
V
, the
HWD
21
11 supply current draw will be minimized in
idle mode. Whereas the device will be disabled with shut-
down voltages less than V
DD
, the idle current may be greater
than the typical value of 0.3μA. In either case, the SHUT-
DOWN pin should be tied to a fixed voltage to avoid un-
wanted state changes.
In many applications, a microcontroller or microprocessor
output is used to control the shutdown circuitry. This provides
a quick, smooth shutdown transition. Another solution is to
use a single-pole, single-throw switch in conjunction with an
external pull-up resistor. When the switch is closed, the
SHUTDOWN pin is connected to ground and enables the
amplifier. If the switch is open, the external pull-up resistor,
R
, will disable the
HWD
21
11. This scheme guarantees that
the SHUTDOWN pin will not float, thus preventing unwanted
state changes.
PROPER SELECTION OF EXTERNAL COMPONENTS
Selection of external components when using integrated
power amplifiers is critical for optimum device and system
performance. While the
HWD
21
11 is tolerant of external com-
ponent combinations, consideration must be given to the
external component values that maximize overall system
quality.
The
HWD
21
11’s unity-gain stability allows a designer to maxi-
mize system performance. Low gain settings maximize
signal-to-noise performance and minimizes THD+N. Low
gain configurations require large input signals to obtain a
given output power. Input signals equal to or greater than 1
Vrms are available from sources such as audio codecs.
Please refer to the section,
Audio Power Amplifier Design,
for a more complete explanation of proper gain selection.
12