參數(shù)資料
型號(hào)： HY29LV160TT-12I
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory
中文描述： 1M X 16 FLASH 2.7V PROM, 120 ns, PDSO48
封裝： TSOP-48
文件頁(yè)數(shù)： 23/48頁(yè)
文件大?。?/td> 517K
代理商： HY29LV160TT-12I
23
Rev. 1.2/May 01
HY29LV160
For both of these conditions, the host must issue
a Reset command to return the device to the Read
mode.
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a
‘
0
’
to a
‘
1
’
. Refer to the
“
Sector Erase Command
”
section for additional information. Note that the
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a
‘
1
’
,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a
‘
0
’
, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
HARDWARE DATA PROTECTION
The HY29LV160 provides several methods of pro-
tection to prevent accidental erasure or program-
ming which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 6. This
provides data protection against inadvertent writes.
Low V
CC
Write Inhibit
To protect data during V
CC
power-up and power-
down, the device does not accept write cycles
when V
CC
is less than V
LKO
(typically 2.4 volts). The
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until V
CC
is greater
than V
LKO
. The system must provide the proper
signals to the control pins to prevent unintentional
writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = V
IL
, CE# = V
IH
, or
WE# = V
IH
. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to the Read mode on power-
up.
Sector Protection
Additional data protection is provided by the
HY29LV160
’
s sector protect feature, described
previously, which can be used to protect sensitive
areas of the Flash array from accidental or unau-
thorized attempts to alter the data.
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