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參數(shù)資料
| 型號(hào)： | HY51VS17403HG |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 4M x 4Bit EDO DRAM |
| 中文描述： | 4米× 4位EDO公司的DRAM |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 96K |
| 代理商： | HY51VS17403HG |
HY51V(S)17403HG/HGL
Rev.0.1/Apr.01
5
CAPACITANCE
(Vcc=3.3V +/-10%, TA=25
°
C
)
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /CAS = V
IH
to disable D
out
AC CHARACTERISTICS
(Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 18)
Read, Write, Read-modify-Write and Refresh Cycle
Parameter
Symbol
Min.
Max
Unit
Note
Input capacitance (Address)
CI1
-
5
pF
1
Input capacitance (Clocks)
CI2
-
7
pF
1
Output capacitance (Data-in, Data-out)
CI/O
-
7
pF
1, 2
Parameter
Symbol
-50
-60
-70
Unit
Note
Min
Max
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
-
104
-
124
-
ns
/RAS precharge time
t
RP
30
-
40
-
50
-
ns
/CAS precharge time
t
CP
8
-
10
-
13
-
ns
/RAS pulse width
t
RAS
50
10,000
60
10,000
70
10,000
ns
/CAS pulse width
t
CAS
8
10,000
10
10,000
13
10,000
ns
Row address set-up time
t
ASR
0
-
0
-
0
-
ns
Row address hold time
t
RAH
8
-
10
-
10
-
ns
Column address set-up time
t
ASC
0
-
0
-
0
-
ns
Column address hold time
t
CAH
8
-
10
-
13
-
ns
/RAS to /CAS delay time
t
RCD
12
37
14
45
14
52
ns
3
/RAS to Column address delay time
t
RAD
10
25
12
30
12
35
ns
4
/RAS hold time
t
RSH
10
-
13
-
13
-
ns
/CAS hold time
t
CSH
35
-
40
-
45
-
ns
/CAS to /RAS precharge time
t
CRP
5
-
5
-
5
-
ns
Test Condition
Input rise and fall times = 2ns
Input levels : V
IL
=0V, V
IH
=3V
Input timing reference level : V
IL
/V
IH
= 0.8/2.0V
Output timing reference level :
V
OL
/V
OH
=0.8/0.2V
Output load : 1 TTL gate + C
L
(100pF)
( including scope and jig )
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