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參數(shù)資料
| 型號(hào)： | HY57V56820CLT-K |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 8M x 8Bit Synchronous DRAM |
| 中文描述： | 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.875 X 0.400 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | HY57V56820CLT-K |
HY57V56820C(L)T
Rev. 0.4 / July 2003
7
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Parameter
Symbol
-6
-K
-H
-8
-P
-S
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
System Clock Cycle
Time
CAS Latency = 3
tCK3
6
1000
7.5
1000
7.5
1000
8
1000
10
1000
10
1000
ns
CAS Latency = 2
tCK2
7.5
7.5
10
10
10
12
ns
Clock High Pulse Width
tCHW
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Access Time From
Clock
CAS Latency = 3
tAC3
-
5.4
-
5.4
-
5.4
-
6
-
6
-
6
ns
2
CAS Latency = 2
tAC2
-
6
-
5.4
-
6
-
6
-
6
-
6
ns
Data-Out Hold Time
tOH
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input Setup Time
tDS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address Setup Time
tAS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address Hold Time
tAH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE Setup Time
tCKS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE Hold Time
tCKH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command Setup Time
tCS
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command Hold Time
tCH
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
ns
CLK to Data Output
in High-Z Time
CAS Latency = 3
tOHZ3
2.7
5.4
2.7
5.4
2.7
5.4
3
6
3
6
3
6
ns
CAS Latency = 2
tOHZ2
2.7
5.4
2.7
5.4
3
6
3
6
3
6
3
6
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V56820CLT-P | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-S | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT-6 | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT-8 | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT-H | 4 Banks x 8M x 8Bit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V56820CLT-P | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CLT-S | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32Mx8|3.3V|8K|6/K/H/8/P/S|SDR SDRAM - 256M |
| HY57V56820CT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820CT-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 8M x 8Bit Synchronous DRAM |
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