參數(shù)資料
型號: HY5DU12422BLT-H
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁數(shù): 5/31頁
文件大?。?/td> 686K
代理商: HY5DU12422BLT-H
Rev. 1.1 / Apr. 2006
13
1HY5DU12422B(L)T
HY5DU12822B(L)T
HY5DU121622B(L)T
8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low
Power-Up Sequence
CODE
NOP
PRE
MRS
EMRS
PRE
NOP
MRS
AREF
ACT
RD
VDD
VDDQ
VTT
VREF
/CLK
CLK
CKE
CMD
DM
ADDR
A10
BA0, BA1
DQS
DQ'S
LVCMOS Low Level
tIS tIH
tVTD
T=200usec
tRP
tMRD
tRP
tRFC
tMRD
tXSRD*
READ
Non-Read
Command
Power UP
VDD and CK stable
Precharge All
EMRS Set
MRS Set
Reset DLL
(with A8=H)
Precharge All
2 or more
Auto Refresh
MRS Set
(with A8=L)
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
tMRD
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