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參數(shù)資料
| 型號： | HY5DU12422CTP |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CAP .0047UF 16V PPS FILM 0805 2% |
| 中文描述： | 產(chǎn)品512Mb DDR SDRAM |
| 文件頁數(shù)： | 9/31頁 |
| 文件大?。?/td> | 253K |
| 代理商： | HY5DU12422CTP |
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Rev. 1.0 / Mar. 2005
9
1
HY5DU12422C(L)TP
HY5DU12822C(L)TP
HY5DU121622C(L)TP
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/ AP
BA
Extended Mode Register Set
1,2
H
X
L
L
L
L
OP code
Mode Register Set
1,2
H
X
L
L
L
L
OP code
Device Deselect
1
H
X
H
X
X
X
X
No Operation
1
L
H
H
H
Bank Active
1
H
X
L
L
H
H
RA
V
Read
1
H
X
L
H
L
H
CA
L
V
Read with Autoprecharge
1,3
H
Write
1
H
X
L
H
L
L
CA
L
V
Write with Autoprecharge
1,4
H
Precharge All Banks
1,5
H
X
L
L
H
L
X
H
X
Precharge selected Bank
1
L
V
Read Burst Stop
1
H
X
L
H
H
L
X
Auto Refresh
1
H
H
L
L
L
H
X
Self Refresh
1
Entry
H
L
L
L
L
H
X
Exit
L
H
H
X
X
X
L
H
H
H
Precharge Power
Down Mode
1
Entry
H
L
H
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
L
H
H
H
Active Power
Down Mode
1
Entry
H
L
H
X
X
X
X
L
V
V
V
Exit
L
H
X
Note:
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting
during
Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Precharge command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been
completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
*For more information about Truth Table, refer to “Device Operation” section in Hynix website.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU12422CTP-X | 512Mb DDR SDRAM |
| HY5DU121622CTP-X | 512Mb DDR SDRAM |
| HY5DU12822C | 512Mb DDR SDRAM |
| HY5DU12822CLTP | CERAMIC CAPACITORS NP0 |
| HY5DU12822CTP | 512Mb DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU12422CTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422FP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12422LT-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HY5DU12422LT-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X32MX4|CMOS|TSSOP|66PIN|PLASTIC |
| HY5DU12422LT-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
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