參數(shù)資料
型號(hào): HY5DV651622TC-G55
英文描述: DDR Synchronous DRAM
中文描述: DDR同步DRAM
文件頁數(shù): 19/27頁
文件大?。?/td> 273K
代理商: HY5DV651622TC-G55
Rev. 0.3/May. 02
19
HY5DV281622AT
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
availability of the first burst of output data. The latency can be programmed 3 or 4 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The HY5DV281622A supports Full and Half strength driver intended for lighter load and/or point-to-point environ-
ments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about
50% of Full drive strength.
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