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參數(shù)資料
| 型號： | HY5V16CF |
| 英文描述： | 1Mx16|3.3V|4K|H|SDR SDRAM - 16M |
| 中文描述： | 1Mx16 | 3.3 | 4K的|魔| SDRAM的特別提款權(quán)- 1,600 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 102K |
| 代理商： | HY5V16CF |
HY5V16CF
2 Banks x 512K x 16Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.0/Jun.01
DESCRIPTION
The Hynix HY5V16CF is a 16,777,216-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require
large memory density and high bandwidth. HY5V16CF is organized as 2banks of 524,288x16.
HY5V16CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output volt-
age levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
Note)
All device pins are compatible with LVTTL interface
JEDEC standard 60Ball FD-BGA with 0.65mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable C A S Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
H Y 5 V 1 6 C F - H
1 3 3 M H z
Normal
2Banks x
512Kbits x16
L V T T L
10.1x 6.4 60Ball 0.65
Pin -pitch FD-BGA
H Y 5 V 1 6 C F - S
1 0 0 M H z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5V16CF-H | x16 SDRAM |
| HY5V16CF-S | x16 SDRAM |
| HY6116-10 | x8 SRAM |
| HY6116-12 | x8 SRAM |
| HY6116-15 | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5V16CF-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY5V16CF-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY5V22(L)F(P)-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY5V22(L)F(P)-55 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
| HY5V22(L)F(P)-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 1M x 32Bit Synchronous DRAM |
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