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參數(shù)資料
| 型號(hào)： | HY62UF16804A-SM70I |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 512K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | MICRO, BGA-48 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | HY62UF16804A-SM70I |
HY62UF16804A
Rev.10/Jan. 2002
7
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and low /UB and /or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0
°C to 70°C / -40°C to 85°C
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VDR
Vcc for Data Retention
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
1.2
-
3.3
V
LL
-
15
uA
ICCDR
Data Retention Current
Vcc=1.5V, /CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
SL
-
8
uA
TCDR
Chip Deselect to Data
Retention Time
0
-
ns
TR
Operating Recovery Time
See Data Retention Timing Diagram
tRC(2)
-
ns
Notes:
1. Typical values are under the condition of TA = 25
°C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
/CS or
/UB & /LB
VDR
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
tCDR
tR
Vss
VCC
2.7V
VIH
DATA RETENTION MODE
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