參數(shù)資料
型號: HYB 39S16160CT-5.5
廠商: SIEMENS AG
英文描述: 1M × 16-Mbit Synchronous DRAM for High-Speed Graphics Applications(16M位(1M × 16)同步動態(tài)RAM(用于高速圖形場合))
中文描述: 100萬× 16高兆同步DRAM高速圖形應(yīng)用程序(1,600位(1米× 16)同步動態(tài)隨機(jī)存儲器(用于高速圖形場合))
文件頁數(shù): 17/19頁
文件大?。?/td> 110K
代理商: HYB 39S16160CT-5.5
HYB 39S16160CT-5.5/-6/-7
16-MBit Synchronous DRAM
Data Book
17
09.99
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced
to the 1.4 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in Figure below. Specified
t
AC
and
t
OH
parameters are measured with a 30 pF only, without any resistive termination and
with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1ns, a time (
t
T
/2
0.5) ns has to be added to this parameter.
4. If
t
T
is longer than 1 ns, a time (
t
T
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
30 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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