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參數(shù)資料
| 型號： | HYB 39S16160CT-7 |
| 廠商： | SIEMENS AG |
| 英文描述： | 1M × 16-Mbit Synchronous DRAM for High-Speed Graphics Applications(16M位(1M × 16)同步動態(tài)RAM(用于高速圖形場合)) |
| 中文描述： | 100萬× 16高兆同步DRAM高速圖形應用程序（1,600位（1米× 16）同步動態(tài)隨機存儲器（用于高速圖形場合）） |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 110K |
| 代理商： | HYB 39S16160CT-7 |
HYB 39S16160CT-5.5/-6/-7
16-MBit Synchronous DRAM
Data Book
10
09.99
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after a two-clock delay (DQM
Data Disable Latency
t
DQZ
). DQM also provides a data mask function for writes. When it is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency
t
DQW
= zero clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data Read and Write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency
t
CSL
).
Power Down
To reduce standby power consumption, a Power Down mode is available. Bringing CKE low enters
the Power Down mode and all of receiver circuits are gated. All banks must be precharged before
entering this mode. One clock delay is required for mode entry and exit. The Power Down mode
does not perform any refresh operations.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation a time equal to t
WR
(write
recovery time) after the last data in.
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require
a time
t
WR
from the last burst data to apply the precharge command.
Burst Termination
After a burst Read or Write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, using a Precharge Command to interrupt a burst
Bank Selection by Address Bits
A10
A11
Bank A only
Low
Low
Bank B only
Low
High
Both A and B
High
Don’t Care
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S16160CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications |
| HYB39S16160CT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16 MBit Synchronous DRAM |
| HYB39S16320TQ-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation |
| HYB39S16320TQ-5.5 | 制造商:Siemens 功能描述:Electronic Component |
| HYB39S16320TQ-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Special Mode Registers Two color registers Burst Read with Single Write Operation |
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