參數(shù)資料
型號: HYB18T1G160AF-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 1 Gbit DDR2 SDRAM
中文描述: 1千兆位DDR2內(nèi)存
文件頁數(shù): 11/89頁
文件大小: 1261K
代理商: HYB18T1G160AF-3
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 11 Rev. 1.02 May 2004
Block Diagram 32Mbit x 8 I/O x 4 Internal Memory Banks
(64Mb x 8 Organisation with 14 Row, 3 Bank and 11 Column External Addresses)
RAS
AP
CAS
CK
CS
WE
CK
C
Column-Address
Counter/Latch
Mode
Registers
10
C
D
A0-A13,
BA0-BA2
CKE
17
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(16384 x256x32)
Sense Amplifiers
Bank0
Bank1
Bank7
17
8
2
2
2
R
32
COL0,1
DQ0-DQ7,
DM
DQS
DQS
Column
Decoder
(256
R
1
8
B
R
&
16384
A
B
17
R
1
DQS
DQS
CK, CK
DLL
8
8
8
8
8
Input
Register
1
1
1
1
1
32
4
32
Data
Mask
Data
CK,
CK
COL0,1
COL0,1
M
DQS
Generator
1
1
8
32
R
Write
FIFO
Dri&
D
1
1
8
8
8
8
8
8
8
8
17
8
8
Note:
This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note:
DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
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