參數(shù)資料
型號: HYB18T1G400AFL-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 1 Gbit DDR2 SDRAM
中文描述: 1千兆位DDR2內(nèi)存
文件頁數(shù): 25/89頁
文件大?。?/td> 1752K
代理商: HYB18T1G400AFL-3
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 25 Rev. 1.02 May 2004
ODT Timing for Active and Standby
(Idle) Modes
(Synchronous ODT timings)
ODT Timing for Precharge Power-Down and Active Power-Down Mode (with slow exit)
(Asynchronous ODT timings)
3) ODT turn off time min. (tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is
when the bus is in high impedance. Both are measured from tAOFD.
1) Synchronous ODT timings apply for Active Mode and Standby Mode with CKE “high” and for the “Fast Exit” Active Power Down
Mode (MRS bit A12 set to “0”).
In all these modes the on-die DLL is enabled.
2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on
time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND.
CKE
DQ
ODT01
ODT
CK, CK
see note 1
Rtt
tAOF(min)
tAON(min)
tAON(max)
tAOF(max)
tAOND (2 tck)
tAOFD (2.5 tck)
t
IS
t
IS
T0
T1
T2
T3
T4
T5
T6
T7
T8
1) Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active Power Down Mode (MRS bit A12 set to
“1”), where the on-die DLL is disabled in this mode of operation.
tAOFPD,min
tAOFPD,max
CKE
DQ
ODT
ODT02
CK, CK
"low"
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
IS
t
IS
Rtt
tAONPD,min
tAONPD,max
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