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參數(shù)資料
| 型號(hào)： | HYB18T1G800AFL-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 14/89頁 |
| 文件大?。?/td> | 1752K |
| 代理商： | HYB18T1G800AFL-5 |
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Page 14 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
2.2 Basic Functionality
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and con-
tinue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an
Activate command, which is followed by a Read or Write command. The address bits registered coincident with
the activate command are used to select the bank and row to be accessed (BA0 ~ BA2 select one of the eight
banks, A0-A13 select the row for x4 and x8 components, A0~A12 select the row for x16 components). The
address bits registered coincident with the Read or Write command are used to select the starting column location
for the burst access and to determine if the Auto-Precharge command is to be issued. Prior to normal operation,
the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initial-
ization, register definition, command description and device operation.
2.2.1 Power On and Initialization
DDR2 SDRAM’s must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 * VDDQ and ODT at a low state (all other inputs may be
undefined). To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. Maximum
power up interval for VDD/VDDQ is specified as 10.0 ms. The power interval is defined as the amount of time it takes
for VDD / VDDQ to power-up from 0V to 1.8 V +/- 100 mV.
- VDD,VDDL and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95 V max, AND
- VREF tracks VDDQ/2
or
- Apply VDD before or at the same time as VDDL,
- Apply VDDL before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & VREF.
at least one of these two sets of conditions must be met.
2. Start clock (CK, CK) and maintain stable power and clock condition for a minimum of 200 μs.
3. Apply NOP or Deselect commands & take CKE high.
4. Wait minimum of 400ns, then issue a Precharge-all command.
5. Issue EMRS(2) command. (To issue EMRS(2) command, provide “l(fā)ow” to BA0 and BA2 and “high” to BA1)
6. Issue EMRS(3) command. (To issue EMRS(3) command, provide “l(fā)ow” to BA2 and “high” to BA0 and BA1)
7. Issue EMRS(1) command to enable DLL. (To issue “DLL Enable” command, provide “l(fā)ow” to A0 and
“high” to BA0 and “l(fā)ow” to BA1,BA2 and A13~A15)
8. Issue MRS command (Mode Register Set) for ’DLL reset’. (To issue DLL reset command, provide “high” to A8
and “l(fā)ow” to BA0 ~ BA2 and A13 ~ A15)
9. Issue Precharge-all command.
10. Issue 2 or more Auto-Refresh commands.
11. Issue a MRS command with low on A8 to initialize device operation. (i.e. to program operating parameters with
out resetting the DLL)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD calibration
is not used, EMRS OCD Default command (A9=A8=A7=1) followed by EMRS(1) OCD Calibration Mode
Exit command (A9=A8=A7=0) must be issued with other parameters of EMRS(1).
13. The DDR2 SDRAM is now ready for normal operation.
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| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
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