參數(shù)資料
型號: HYB3117400BJ-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: Driver IC; Number of Drivers:8; Package/Case:18-DIP; Driver Type:Darlington; Output Current:750mA; Mounting Type:Through Hole; Supply Voltage:5V
中文描述: 4M X 4 FAST PAGE DRAM, 60 ns, PDSO26
封裝: 0.300 INCH, PLASTIC, SO-26
文件頁數(shù): 8/26頁
文件大?。?/td> 253K
代理商: HYB3117400BJ-60
Semiconductor Group
8
HYB 3116(7)400BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
AC Characteristics
5)6)
16F
T
A
= 0 to 70 °C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
common parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
90
110
130
ns
RAS precharge time
30
40
50
ns
RAS pulse width
50
10k
60
10k
70
10k
ns
CAS pulse width
13
10k
15
10k
20
10k
ns
Row address setup time
0
0
0
ns
Row address hold time
Column address setup time
8
0
10
0
10
0
ns
ns
Column address hold time
10
15
15
ns
RAS to CAS delay time
18
37
20
45
20
50
RAS to column address delay
time
13
25
15
30
15
35
ns
RAS hold time
CAS hold time
t
RSH
t
CSH
t
CRP
t
T
t
REF
t
REF
t
REF
13
50
15
60
20
70
ns
ns
CAS to RAS precharge time
5
5
5
ns
Transition time (rise and fall)
3
50
3
50
3
50
ns
7
Refresh period for HYB3117400
32
32
32
ms
Refresh period for HYB3116400
64
64
64
ms
Refresh period for L-version
256
256
256
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
50
60
70
ns
8, 9
Access time from CAS
13
15
20
ns
8, 9
Access time from column address
t
AA
OE access time
25
30
35
ns
8,10
t
OEA
13
15
20
ns
Column address to RAS lead time
t
RAL
Read command setup time
25
30
35
ns
t
RCS
t
RCH
t
RRH
0
0
0
ns
Read command hold time
0
0
0
ns
11
Read command hold time
referenced to RAS
0
0
0
ns
11
相關PDF資料
PDF描述
HYB3117400BT-50 3.3V 4M x 4-Bit Dynamic RAM
HYB3116400BT-50 3.3V 4M x 4-Bit Dynamic RAM
HYB3116400BTL-60 3.3V 4M x 4-Bit Dynamic RAM
HYB3164160AT-60 4M x 16-Bit Dynamic RAM
HYB3165160AT-60 4M x 16-Bit Dynamic RAM
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