參數(shù)資料
型號(hào): HYB314265BJL-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 256K x 16-Bit EDO-Dynamic RAM
中文描述: 256K X 16 EDO DRAM, 50 ns, PDSO40
文件頁(yè)數(shù): 7/28頁(yè)
文件大?。?/td> 1324K
代理商: HYB314265BJL-50
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
7
Capacitance
T
A
= 0 to 70
°
C;
f
= 1 MHz
Average
V
CC
supply current during
RAS-only refresh cycles:
-45 version
-50 version
I
CC3
105
95
mA
2, 4
Average
V
CC
supply current during hyper page
mode (EDO) operation:
-45 version
-50 version
I
CC4
75
65
mA
2, 3, 4
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
CC
– 0.2 V)
Standby
V
CC
supply current (L-version only)
(RAS = LCAS = UCAS = WE =
V
CC
– 0.2 V)
Average
V
CC
supply current during CAS-
before-RAS refresh mode:
I
CC5
1
mA
1
I
CC5
200
μ
A
1
-45 version
-50 version
I
CC6
105
95
mA
2, 4
Self Refresh Current (L-version only)
CBR cycle with RAS >trasss(min), CAS held low;
WE =
V
CC
– 0.2 V,
Addresses and Din =
V
CC
– 0.2 V or 0.2 V
I
CC7
250
μ
A
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A8)
C
I
1
C
I
2
C
I
O
5
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE)
7
pF
Output capacitance (l/O1 to l/O16)
7
pF
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
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