參數(shù)資料
型號(hào): HYB3164405AT-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: High-Speed Fully-Differential Amplifiers 8-SOIC 0 to 70
中文描述: 16M X 4 EDO DRAM, 50 ns, PDSO32
文件頁(yè)數(shù): 10/32頁(yè)
文件大?。?/td> 473K
代理商: HYB3164405AT-50
Semiconductor Group
98
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
CAS to output in low-Z
t
CLZ
t
OFF
t
OEZ
t
DZC
t
DZO
t
CDD
t
ODD
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
Output buffer turn-off delay from OE
0
13
0
15
ns
12
Data to CAS low delay
0
0
ns
13
Data to OE low delay
0
0
ns
13
CAS high to data delay
13
15
ns
14
OE high to data delay
13
15
ns
14
Write Cycle
Write command hold time
t
WCH
t
WP
t
WCS
t
RWL
t
CWL
t
DS
t
DH
8
10
ns
Write command pulse width
7
10
ns
Write command setup time
0
0
ns
15
Write command to RAS lead time
8
10
ns
Write command to CAS lead time
8
10
ns
Data setup time
0
0
ns
16
Data hold time
7
10
ns
16
Read-modify-Write Cycle
Read-write cycle time
t
RWC
t
RWD
t
CWD
t
AWD
t
OEH
111
135
ns
RAS to WE delay time
67
79
ns
15
CAS to WE delay time
30
34
ns
15
Column address to WE delay time
42
49
ns
15
OE command hold time
7
10
ns
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
t
HPC
t
CP
t
CPA
t
COH
t
RAS
20
25
ns
CAS precharge time
8
10
ns
Access time from CAS precharge
27
35
ns
7
Output data hold time
5
5
ns
RAS pulse width in hyper page mode
50
200k
60
200k
ns
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 C,
V
CC
= 3.3 V
±
0.3V ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
相關(guān)PDF資料
PDF描述
HYB3164405BJ High-Speed Fully-Differential Amplifiers 8-SOIC 0 to 70
HYB3164405J High-Speed Fully-Differential Amplifiers 8-SOIC -40 to 85
HYB3164405T-50 16M x 4-Bit Dynamic RAM
HYB3164405T-60 High-Speed Fully-Differential Amplifiers 8-MSOP -40 to 85
HYB3165405AT-50 Wideband, Low Distortion Fully Differential Amplifier with Shutdown 8-MSOP-PowerPAD -40 to 85
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