參數(shù)資料
型號: HYM72V1005GU-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
中文描述: 1M X 72 EDO DRAM MODULE, 50 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 9/14頁
文件大?。?/td> 74K
代理商: HYM72V1005GU-50
HYM 64(72)V1005GU-50/-60
1M x 64/72 DRAM Module
Semiconductor Group
9
AC Characteristics
5)6)
T
A
= 0 to 70 °C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
16E
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
84
104
ns
RAS precharge time
30
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
8
10k
10
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
8
10
ns
RAS to CAS delay time
12
37
14
45
ns
RAS to column address delay
RAS hold time
10
13
25
12
15
30
ns
ns
CAS hold time
40
50
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
1
50
1
50
ns
7
Refresh period
16
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
t
RAL
t
RCS
t
RCH
t
RRH
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8,10
OE access time
13
15
ns
Column address to RAS lead time
25
30
ns
Read command setup time
0
0
ns
Read command hold time
0
0
ns
11
Read command hold time referenced to
RAS
0
0
ns
11
CAS to output in low-Z
t
CLZ
t
OFF
t
OEZ
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
Output turn-off delay from OE
0
13
0
15
ns
12
相關(guān)PDF資料
PDF描述
HYM64V1005GU-5 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
HYM64V1005GU-50 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
HYM64V1005GU-60 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
HYM72V1005GU-60 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module
HYM72V1600GS-50 16M x 72-Bit Dynamic RAM Module
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