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參數(shù)資料
| 型號： | HYM72V2005GS-50- |
| 廠商： | SIEMENS AG |
| 英文描述： | 2M x 72-Bit EDO-DRAM Module |
| 中文描述： | 200萬× 72位江戶記憶體模組 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 66K |
| 代理商： | HYM72V2005GS-50- |
Semiconductor Group
5
HYM72V2005GS-50/-60
2M x 72-ECC Module
Absolute Maximum Ratings
Operating temperature range .........................................................................................
Storage temperature range......................................................................................
Input/output voltage ............................................................................... -0.5 to min (Vcc+0.5, 4.6) V
Power supply voltage.................................................................................................
Power dissipation....................................................................................................................
Data out current (short circuit) ................................................................................................
0 to + 70 °C
– 55 to + 125 °C
– 0.5V to 4.6 V
5,8 W
50 mA
Note
: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 °C;
V
CC
= 3.3 V
±
0.3 V
Parameter
Symbol
Limit Values
Unit
Test
Condition
min.
max.
Input high voltage
V
IH
V
IL
V
OH
2.0
Vcc + 0.3 V
1)
Input low voltage
Output high voltage (LVTTL)
Output H“l(fā)evel voltage (
I
OUT
= – 2 mA)
Output low voltage (LVTTL)
Output L“l(fā)evel voltage (
I
OUT
= + 2 mA)
Output high voltage (LVCMOS)
Output H“l(fā)evel voltage (
I
OUT
= – 100
μ
A)
Output low voltage (LVCMOS)
Output L“l(fā)evel voltage (
I
OUT
= + 100
μ
A)
Input leakage current
(0 V <
V
IN
< Vcc, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< Vcc)
Average
V
CC
supply current:
– 0.3
2.4
0.8
–
V
V
1)
1)
V
OL
–
0.4
V
1)
V
OH
Vcc-0.2
–
V
1)
V
OL
–
0.2
V
1)
I
I(L)
– 20
20
μ
A
1)
I
O(L)
– 20
20
μ
A
1)
-50 version
-60 version
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.)
Standby
V
CC
supply current
(RAS = CAS =
2.4V
,
one address change
within 15,6
μ
s trc )
I
CC1
–
–
1080
990
mA
mA
2) 3) 4)
I
CC2
–
50
mA
–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYM72V4000GS-50 | 4M x 72-Bit Dynamic RAM Module |
| HYM72V4010GS-50 | Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| HYM72V4000GS-50- | 4M x 72-Bit Dynamic RAM Module |
| HYM72V4010GS-60 | 4M x 72-Bit Dynamic RAM Module |
| HYM72V4000GS-60 | 4M x 72-Bit Dynamic RAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYM72V2005GS-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 72-Bit EDO-DRAM Module |
| HYM72V2005GU-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module |
| HYM72V2005GU-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 2M x 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module |
| HYM72V2005GU-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HYM72V32636BLT8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32Mx64|3.3V|K/H|x8|SDR SDRAM - Unbuffered DIMM 256MB |
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