Page 4
Rev. 0.0/ Feb. 99
Preliminary
HYMR11648/11848 Series
RCMD
B59
I
V
CMOS
Serial Command Input. Pin used to read from and write
to the control registers. Also used for power manage-
ment.
RCOL4..
RCOL0
A73, B73, A71, B71, A69
I
RSL
Column bus. 5-pin bus containing control and address
information for column accesses.
RCTM
A79
I
RSL
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RCTMN
A81
I
RSL
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
RDQA8..
RDQA0
A91, B91, A89, B89, A87, B87, A85,
B85, A83
I/O
RSL
Data bus A. A 9-pin bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQA8 is
non-functional on x16 devices.
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQB8 is
non-functional on x16 devices.
RROW2..
RROW0
B77, A75, B75
I
RSL
Row bus. 3-pin bus containing control and address infor-
mation for row accesses.
RSCK
A59
I
V
CMOS
Clock input. Pin used to read from and write to the con-
trol registers.
SA0
B53
I
SV
DD
Serial Presence Detect Address 0.
SA1
B55
I
SV
DD
Serial Presence Detect Address 1.
SA2
B57
I
SV
DD
Serial Presence Detect Address 2.
SCL
A53
I
SV
DD
Serial Presence Detect Clock.
SDA
A55
I/O
SV
DD
Serial Presence Detect Data (Open Collector I/O).
SIN
B36
I/O
V
CMOS
Serial I/O. Pin for reading from and writing to the control
registers. Attaches to SIO0 of the first RDRAM on the
module.
SOUT
A36
I/O
V
CMOS
Serial I/O. Pin for reading from and writing to the control
registers. Attaches to SIO1 of the last RDRAM on the
module.
SV
DD
A56, B56
SPD Voltage. Used for signals SCL, SDA, SWE, SA0,
SA1 and SA2.
SWP
A57
I
SV
DD
Serial Presence Detect Write Protect (active high). When
low, the SPD can be written as well as read.
V
CMOS
A35, B35, A37, B37
CMOS I/O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
Vdd
A41, A42, A54, A58, B41, B42, B54,
B58
Supply voltage for the RDRAM core and interface logic.
Vref
A51, B51
Logic threshold reference voltage for RSL signals.
Signal
Pins
I/O
Type
Description