參數(shù)資料
型號(hào): HYMR1616-840
英文描述: RAMBUS DRAM Module
中文描述: Rambus的內(nèi)存
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 111K
代理商: HYMR1616-840
Page 6
Rev. 0.0/ Feb. 99
Preliminary
HYMR11648/11848 Series
Absolute Maximum Ratings
DC Recommended Electrical Conditions
AC Electrical Specifications
Symbol
Parameter
Min
Max
Unit
V
I,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
- 0.3
V
DD
+ 0.3
V
V
DD,ABS
Voltage on VDD with respect to Gnd
- 0.5
V
DD
+ 1.0
V
T
STORE
Storage temperature
- 50
100
°
C
Symbol
Parameter and Conditions
Min
Max
Unit
V
DD
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
V
CMOS
CMOS I/O pin power supply - 2.5V controllers:
- for 1.8V controllers:
2.5 - 0.13
1.8 - 0.1
2.5 + 0.25
1.8 + 0.2
V
V
V
REF
Reference voltage
1.4 - 0.2
1.4 + 0.2
V
V
IL
RSL input low voltage
V
REF
- 0.5
V
REF
- 0.2
V
V
IH
RSL input high voltage
V
REF
+ 0.2
V
REF
+ 0.5
V
V
IL,CMOS
CMOS input low voltage
- 0.3
0.5V
CMOS
- 0.25
V
V
IH,CMOS
CMOS input high voltage
0.5V
CMOS
+ 0.25
V
CMOS
+ 0.3
V
V
OL,CMOS
CMOS output low voltage @ I
OL,CMOS
= 1mA
0.3
V
V
OH,CMOS
CMOS output high voltage @ I
OH,CMOS
= -0.25mA
V
CMOS
- 0.3
V
I
REF
V
REF
current @ V
REF,MAX
-40
40
μ
A
I
SCK,CMD
CMOS input leakage current @ (0
V
CMOS
V
DD
)
-40
40
μ
A
I
SIN,SOUT
CMOS input leakage current @ (0
V
CMOS
V
DD
)
-10.0
10.0
μ
A
Symbol
Parameter and Conditions
Min
Max
Unit
Z
Module Impedance
25.2
30.8
Ohms
T
PD
Propagation Delay, all RSL signals
-
1.2
ns
T
PD
Propagation delay variation of RSL signals with respect to an average clock delay
a
-0.01
0.01
ns
T
PD-CMOS
Propagation delay variation of SCK and CMD signals with respect to an average clock
delay
a
-0.1
0.1
ns
V
α
/V
IN
Attenuation Limit
4.0
%
V
XF
/V
IN
Forward crosstalk coefficient (300ps input risetime 20%-80%)
0.8
%
V
XB
/V
IN
Backward crosstalk coefficient (300ps input risetime 20%-80%)
1
%
a. Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN).
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